Abstract
This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.
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References
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Yan Zongfu received his B.S. degree in computer software from Xi’an Jiaotong University in 1989, and his M.S. degree in computer engineering from People’s University of China in 1992. He is now a Ph.D candidate in computer engineering at the Beijing Institute of Technology. His current research interests include EDA, knowledge-based system and database system.
Liu Mingye is currently a Professor of computer engineering at Beijing Institute of Technology. His research interests are intelligent CAD, ASIC design and VLSI design automation.
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Yan, Z., Liu, M. The RTL binding and mapping approach of VHDL High-level synthesis system HLS/BIT. J. of Comput. Sci. & Technol. 11, 562–569 (1996). https://doi.org/10.1007/BF02951619
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DOI: https://doi.org/10.1007/BF02951619