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DYNAMEM — A microarchitecture for improving memory disambiguation at run-time

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Abstract

This paper presents a new microarchitecture technique named DYNAMEM, in which memory reference instructions are dynamically scheduled and can be executed out-of-order. Load instructions can bypass store instructions speculatively, even if the store instructions’ addresses are unknown. DYNAMEM can greatly alleviate the restraints of ambiguous memory dependencies. Simulation results show that the frequency of false load is low. Mechanism has been provided to repair false loads with low penalty, and to achieve precise interrupts. Discussions and experimental results show that DYNAMEM could dramatically raise instruction-level parallelism in programs without recompilation.

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This research was supported by the National Natural Science Foundation of China.

Wang Xianzhu received his B.S. degree in computer science from Tsinghua University in 1992. He is now a Ph.D. candidate in the Department of Computer Science and Technology, Tsinghua University. His research interests include processor microarchitecture and instruction-level parallelism.

Liao Heng received his B.S. degree in computer science from Tsinghua University in 1991. He is now a Ph.D. candidate in the Department of Computer Science and Technology, Tsinghua University. His research interests include processor microarchitecture and highperformance interconnection.

Li Sanli is an Academician of Chinese Academy of Engineering, and a Professor in the Department of Computer Science and Technology, Tsinghua University. His research interests include network parallel computing, processor architecture and instruction-level parallelism.

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Wang, X., Liao, H. & Li, S. DYNAMEM — A microarchitecture for improving memory disambiguation at run-time. J. of Comput. Sci. & Technol. 11, 589–600 (1996). https://doi.org/10.1007/BF02951622

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  • DOI: https://doi.org/10.1007/BF02951622

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