Abstract
This paper studies the realization of the high level synthesis from system behavioral (algorithmic or functional) description of circuits to structural description of RTL and logic level. Based on Xilinx-FPGA library, the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated. The main points in this paper include the technical decision of each sub-system in a VHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC 2, and correct running results are given.
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References
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This work is supported by the National Natural Science Foundation of China, National “Eighth Five-Year-Plan” Scince Research Project and National Defense Science Foundation.
LIU Mingye is a Professor and Ph.D. tutor of ASIC Research Center of Beijing Institute of Technology (BIT). He is engaged in research and education of EDA. His main research fieds include hardware description language, high level synthesis, logic synthesis and simulation.
ZHANG Dongxiao is working at ASIC Research Center of BIT. He received his Ph.D. degree in computer application from BIT in 1999. His fields of research include VHDL, high level synthesis and simulation.
XU Qingping graduated from BIT in 1997 and received his Ph.D. degree in computer application. His main research interests are VHDL and formal verification.
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Liu, M., Zhang, D. & Xu, Q. Technical decisions on several key problems in VHDL high level synthesis system. J. Comput. Sci. & Technol. 14, 565–571 (1999). https://doi.org/10.1007/BF02951876
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DOI: https://doi.org/10.1007/BF02951876