Abstract
In this paper a new scheme for mixed mode scan-based BIST is presented with complete fault coverage, and some new concepts of folding set and computing are introduced. This scheme applies single feedback polynomial of LFSR for generating pseudo-random patterns, as well as for compressing and extending seeds of folding sets and an LFSR, where we encode seed of folding set as an initial seed of LFSR. Moreover these new techniques are 100% compatible with scan design. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs.
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References
Abramovici M, Breuer M, Friedman A. Digital Systems Testing and Testing and Testable Design. New York: Computer Science Press (W. H. Freeman and Co.), 1990.
Chen K-T, Lin C-J. Timing driven test point insertion for full-scan and partial-scan BIST. InProceedings IEEE International Test Conference, Washington DC, 1995, pp.506–514.
Savaria Y, Yousef M, Kaminska B, Koudil M. Automatic test point insertion for pseudo-random testing. InProceedings of International Symposium on Circuits and Systems, 1991, pp.1960–1963.
Williams M J Y, Angell J B. Enhancing testability of large-scale integrated circuits via test points and additional logic.IEEE Transactions on Computers, January, 1973, C-22(1): 46–60.
Brglez Fet al. Hardware-based weighted random pattern generation for boundary-scan. InProceedings of IEEE International Test Conference, Washington DC, 1989, pp.264–274.
Strle A, Wunderlich H-J. TESTCHIP: A chip for weighted random pattern generation, evaluation, and test control. InIEEE Journal of Solid State Circuits, July, 1991, 26(7): 1056–1063.
Tsai K-H, Hellebrand S, Marek-Sadowska S, Rajski J. STARBIST: Scan autocorrelated random pattern generation. InProceedings of ACM/IEEE Design Automation Conference, Anaheim CA, June 9–13, 1997.
Wunderlich H-J. Self test using unequiprobable random patterns. InProc. IEEE 17th International Symposium on Fault-Tolerant Computing, FTCS-17, Pittsburgh, 1987, pp.258–263.
Savir J, McAnney William H. A multiple seed linear feedback shift register.IEEE Transactions on Computers, February, 1992, 41(2): 250–252.
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers.IEEE Transactions on Computers, February, 1995, 44(2): 223–233.
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern generation for a deterministic BIST scheme. InProceedings of IEEE/ACM International Conference on CAD-95, San Jose, CA, November, 1995, pp. 88–94.
Koenemann B. LFSR-coded test patterns for scan designs. InProceedings of European Test Conference, Munich, 1991, pp.237–242.
Touba N A, McCluskey E J. Altering a pseudo-random bit sequence for scan-based BIST. InProceedings of IEEE International Test Conference, Washington DC, 1996, pp.167–175.
Kiefer G, Wunderlich H-J. Using BIST control for pattern generation. InProceedings IEEE International Test Conference, Washington DC, November, 1997, pp.347–355.
Wunderlich H-J, Kiefer G. Bit-flipping BIST. InProceedings of ACM/IEEE International Conference on CAD-96 (ICCAD96), San Jose, CA, November, 1996, pp.337–343.
Chakrabarty K, Murray B T. Design of build-in test generator circuits using width compression.IEEE Trans. CAD, Oct., 1998, 17: 1044–1051.
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-mode BIST using embedded processors.Journal of Electronic Testing: Theory and Applications — JETTA, February/April, 1998, 12(1/2): 127–138.
Breuer M A. Design Automation of Digital Systems. New Jersey: Computer Science Press, 1972.
Slavik P. A Tight Analysis of the Greedy Algorithm for Set Cover. In28th Annual ACM STOC’96.
Chvatal V. A greedy heuristic for the set-covering problem.Mathematics of Operations Research, 1979, (4): 233–235.
Li Xiaowei, Paul Y S Cheung, Hideo Fujiwara. ’LFSR-based deterministic TPG for two-pattern testing.Journal of Electronic Testing: Theory and Application, Kluwer Academic Publisher, 2000, 16(5): 419–426.
Brglez Fet al. Accelerated ATPG and fault grading via testability analysis. InProceedings IEEE Int. Symp. on Circuits and Systems, Kyoto, 1985.
Brglez F, Bryan D, Kozminski K. Combinational profiles of sequential benchmark circuits. InProc. IEEE Int. Symp. on Circuits and Systems, 1989, pp.1929–1934.
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This work has been supported by the DFG grant Wu 245/1-3
LIANG Huaguo received the BEng and the MEng degrees in computer science and applications in 1982 and 1989, respectively, from Hefei University of Technology, China. From 1982 to 1998 he worked at Hefei University of Technology, where currently he is an associate professor and also head of the Computer Application Division. Since 1998 he has been working as a guest research fellow at the Division of Computer Architecture, University of Stuttgart, Germany. His research interests include built-in self-test, design automation of digital systems ATPG algorithms, and distributed control.
Sybille Hellebrand received her diploma in mathematics from the University of Regensburg, Germany in 1986. In 1986 she joined the Institute of Computer Design and Fault Tolerance, University of Karlsruhe, where she received the Ph.D. degree in 1991. Then she was a postdoctoral fellow at the TIMA/IMAG-Computer Architecture Group, Grenoble, France. From 1992 to 1996 she worked as an assistant professor at the University of Siegen, Germany. After a sabbatical stay at Mentor Graphics Corp., Wilsonville, Oregon, she joined the Division of Computer Architecture at the University of Stuttgart, Germany in 1997. Since October 1999 she has been a full professor for Applied Computer Science at University of Innsbruck, Austria. Her main research interests include BIST for high quality applications and synthesis of testable systems.
Hans-Joachim Wunderlich received the Dr. rer. nat. (Ph.D.) degree in computer science from the University of Karlsruhe in 1986. There he was head of a research group on automation of circuit design and test from 1986 to 1991. From 1991 to 1996 he was a full professor for computer science at the University of Siegen. Since October 1996 he has been head of the Division for Computer Architecture at the University of Stuttgart. He has been a member of the program committee of numerous conferences and a reviewer of research proposals submitted to NSF and NATO. Within the European projects EUROCHIP and EUROPRACTICE he has been a lecturer for courses on VLSI design and test. Prof. Wunderlich is the author and co-author of three books and over 80 papers in the field of test, synthesis, and fault tolerance of digital systems.
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Liang, H., Hellebrand, S. & Wunderlich, HJ. A mixed-mode BIST scheme based on folding compression. J. Comput. Sci. & Technol. 17, 203–212 (2002). https://doi.org/10.1007/BF02962213
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DOI: https://doi.org/10.1007/BF02962213