Abstract
This paper presents a block turbo decoding algorithm, from its theory to its implementation in a programmable circuit. In this study, we discuss the two prototypes realized. It will be possible to compare the complexity of the core of the process, which is the elementary decoder, thanks to the choice of essential parameters. One prototype is more dedicated to high data rates, the other one being implemented on only one FPGA which means a gain in terms of area.
First, we briefly focus on the description of the siso (Soft-In Soft-out) algorithm used to implement the turbo decoder. Then, we explain the essential choices in order to adapt the algorithm for an ASIC implementation, which leads to a compromise between area and binary error rate. Finally, we present the two prototypes implemented and their experimental results.
Résumé
L’objectif de cet article est de présenter le turbodecodage de codes produits depuis la théorie jusqu’à la réalisation sur circuit programmable. Deux prototypes ont été réalisés, Us serviront de support à cette étude. Il sera en effet possible de comparer la complexité du décodeur élémentaire en fonction d’un certain nombre de paramètres, de mettre face à face une structure dédiée aux débits élevés et une structure optimisée en surface.
Dans une première partie, on trouvera une brève description de l’algorithme srso (Soft-In Soft-Out) permettant de réaliser le turbo décodage. Vient ensuite la description de l’adaptation de cet algorithme à l’implantation sur silicium. Cette phase nécessite des choix entre complexité en terme de circuit et performance en terme de taux d’erreurs binaires. La dernière partie présente les choix d’architectures et les résultats expérimentaux des 2 prototypes.
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Kerouédan, S., Adde, P. & Pyndiah, R. How we implemented block turbo codes?. Ann. Télécommun. 56, 447–454 (2001). https://doi.org/10.1007/BF02995455
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DOI: https://doi.org/10.1007/BF02995455