Abstract
This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10−9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications.
Résumé
Cet article présente les derniers résultats concernant un turbo décodeur de code en blocs. Un circuit turbo décodeur permet la correction d’erreurs dans de petits blocs de données tels que ceux utilisés pour les cellulesAtm avec un rendement proche de 0,5. Une maquette a été développée à l’Enst Bretagne simulant un canal gaussien. Elle permet de mesurer de faibles taux d’erreurs binaires (jusqu’à 10−9) et utilise des circuits intégrés programmables (circuits Xilinx). Le codeBch étendu utilisé comme code élémentaire pour le turbo code et la taille du bloc de données peuvent être modifiés afin de les adapter à différentes applications.
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Adde, P., Pyndiah, R. & Buda, F. Design and performance of a product code turbo encoding-decoding prototype. Ann. Télécommun. 54, 214–219 (1999). https://doi.org/10.1007/BF02998582
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DOI: https://doi.org/10.1007/BF02998582