Abstract
Everlasting demands for solutions to ever growing computation problems and demands for efficient means to manage and utilize sophisticated information have caused an increase in the amount of data necessary to handle a job, while drastic reduction in CPU prices is encouraging massive parallel architectures for gigantic data processing. These trends are increasing the importance of a large shared buffer memory with 103∼104 simultaneously accessible ports. This paper proposes a multiport page buffer architecture that allows 103∼104 concurrent accesses and causes no access conflict nor suspension. It consists of a set of memory banks and multistaged switching networks with controllers that control each row of the networks. Consecutive words in each page are stored orthogonally across banks. Memory interleaving may be applied to improve access rate in consecutive retrievals. When used as a disk cache memory, it decreases the number of disk accesses and increases both the page transfer rate and the maximum number of concurrent page accesses.
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Boral, H. and Dewitt, D. J.: “Database machines: An idea whose time has passed? A critique of the future of database machines,” Database Machines, H. O. Leilich and M. Missikoff (eds.) (Springer-Verlag, Berlin) (1983) 166–187.
Goke, L. R. and Lipovski, G. J.: “Banyan networks for partitioning multiprocessor system,” 1st Annual Symp. on Computer Architecture (Florida) (Jan., 1973) 21–28.
Hockney, R. W. and Josshope, C. R.: Parallel Computers (Adam Hilger Ltd., Bristol) (1981).
Lawrie, D. H.: “Access alignment of data in an array processor,” IEEE Trans. Comput.,C-24 (1975) 1145–1155.
Parker, D. S. Jr.: “Notes on shuffle/exchange-type switching networks,” IEEE Trans. Comput.,C-29 (1980) 213–222.
Pease, M. C.: “The indirect binary n-cube microprocessor array,” IEEE Trans. Comput.,C-26 (1977) 458–473.
Pohm, A. V. and Agrawal, O. P.: High Speed Memory Systems (Reston Publ. Co., Reston) (1983).
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Tanaka, Y. A multiport page-memory architecture and a multiport disk-cache system. NGCO 2, 241–260 (1984). https://doi.org/10.1007/BF03037059
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DOI: https://doi.org/10.1007/BF03037059