Abstract
UNIRED II is the high performance inference processor for the parallel inference machine PIE64. It is designed for the committed choice language Fleng, and for use as an element processor of parallel machines. Its main features are: 1) a tag architecture, 2) three independent memory buses (instruction fetching, data reading, and data writing), 3) a dedicated instruction set for efficient execution of Fleng, 4) multi-context processing for reducing pipeline interlocking and overhead of interprocessor synchronization. With the multi-context processing mechanism, the internal pipeline is shared by several independent instruction streams (contexts), and which contexts are to be executed is determined cycle by cycle. So, UNIRED II acts as a shared-pipeline MIMD processor. In this paper, several architectural features including the multi-context processing and the instruction set are described. Performance measurement results by simulation are also presented. On a 10MHz UNIRED II, 920K Reduction Per Second has been achieved, and it is shown that the multi-context processing mechanism is very effective for improved performance.
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Kentaro Shimada, Ph. D.: He was born in Okayama on June 16, 1964, and has grown up in Tokyo, Japan. He received the degrees of Bachelor of Electrical Engineering, Master of Information Engineering and Doctor of Information Engineering form the University of Tokyo in 1988, 1990, 1993, respectively. His current research interests are in computer architecture, processor design, and parallel programming languages. He is a member of Information Processing Society of Japan.
Hanpei Koike, Ph. D.: He was born in Kamakura, Japan on June 15, 1961. He received the degrees of Bachelor of Electronics Engineering, Master of Information Engineering and Doctor of Information Engineering from the University of Tokyo in 1984, 1986 and 1990, respectively. In 1989, he joined the faculty of Engineering, University of Tokyo, where he is now a lecturer. His current research interests are in computer architecture, parallel programming, and system software. He is a menber of IEEE, ACM, Information Processing Society of Japan, and Japan Society for Software Science and Technology.
Hidehiko Tanaka, Ph. D.: He was born in Hyogo, Japan on January 15, 1943. He received the degrees of Bachelor of Electronics Engineering, Master of Electrical Engineering and Doctor of Electrical Engineering from the University of Tokyo in 1965, 1967 and 1970, respectively. In 1970, he joined the faculty of Engineering, University of Tokyo, where he is now a professor. From 1978 to 1979, he was a visiting professor of City College of New York, NY. His current research interests are in computer architecture, distributed systems, CAD system for LSI design, and artificial intelligence. He is a member of IEEE, ACM, Information Processing Society of Japan, and IECE of Japan.
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Shimada, K., Koike, H. & Tanaka, H. UNIRED II: The high performance inference processor for the parallel inference machine PIE64. New Gener Comput 11, 251–269 (1993). https://doi.org/10.1007/BF03037178
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DOI: https://doi.org/10.1007/BF03037178