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CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog

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  • Parallel Machine Architecture
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Abstract

CARMEL-2 is a high performance VLSI uniprocessor, tuned forFlat Concurrent Prolog (FCP). CARMEL-2 shows almost 5-fold speedup over its predecessor, CARMEL-1, and it achieves 2,400 KLIPS executingappend. This high execution rate was gained as a result of an optimized design, based on an extensive architecture-oriented execution analysis of FCP, and the lessons learned with CARMEL-1. CARMEL-2 is a RISC processor in its character and performance. The instruction set includes only 29 carefully selected instructions. The 10 special instructions, the prudent implementation and pipeline scheme, as well as sophisticated mechanisms such as intelligent dereference, distinguish CARMEL-2 as a RISC processor for FCP.

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Authors and Affiliations

  1. Department of Electrical Engineering, Department of Computer Science, Technion-Israel Institute of Technology, Mt. Carmel., 32000, Haifa, Israel

    Arie Harsat & Ran Ginosar

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  1. Arie Harsat
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  2. Ran Ginosar
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Harsat, A., Ginosar, R. CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. NGCO 7, 197–218 (1990). https://doi.org/10.1007/BF03037206

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  • DOI: https://doi.org/10.1007/BF03037206

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