Skip to main content
Log in

A wide instruction word architecture for parallel execution of logic programs coded in BSL

  • Special Issue
  • Parallel Machine Architecture
  • Published:
New Generation Computing Aims and scope Submit manuscript

Abstract

This paper begins by describing BSL, a new logic programming language fundamentally different from Prolog. BSL is a nondeterministic Algol-class language whose programs have a natural translation to first order logic; executing a BSL program without free variables amounts to proving the corresponding first order sentence. A new approach is proposed for parallel execution of logic programs coded in BSL, that relies on advanced compilation techniques for extracting fine grain parallelism from sequential code. We describe a new “Very Long Instruction Word” (VLIW) architecture for parallel execution of BSL programs. The architecture, now being designed at the IBM Thomas J. Watson Research Center, avoids the synchronization and communication delays (normally associated with parallel execution of logic programs on multiprocessors), by determining data dependences between operations at compile time, and by coupling the processing elements very tightly, via a single central shared register file. A simulator for the architecture has been implemented and some simulation results are reported in the paper, which are encouraging.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Cohen, J., “Non-deterministic algorithms,”Computing Surveys,Vol. 11,No. 2, June, 1979.

  2. Conery, J. S., “The AND/OR Process Model for Parallel Interpretation of Logic Programs,”Ph. D. thesis andTechnical Report 204, The University of California, Irvine, 1983.

    Google Scholar 

  3. Cytron, R. G., “Comple-time Scheduling and Optimization for Asynchronous Machines,”Report, No. UIUCDCS-R-84-1177, Dept. of Computer Science, University of Illinois, Urbana-Champaign, October, 1984.

    Google Scholar 

  4. Date, C. J.,Introduction to Database Systems, Addison-Wesley, 1977.

  5. Davies J. R. B., “Parallel Loop Constructs For Multiprocessors,”Report, No. UIUDCS-R-81-1070, Dept of Computer Science, University of Illinois, Urbana-Champaign, May, 1981.

    Google Scholar 

  6. de Bakker, J.,Mathematical Theory of Program Correctness, North Holland, 1979.

  7. Ebcioĝlu, K., “Report on the CHORAL project: An Expert System for Harmonizing Four-part Chorales,”Research Report, RC 12628, IBM Thomas J. Watson Research Center, Yorktown Heights, March, 1987. (This is a revised version of the author’s Ph. D. dissertation, “An Expert System for Harmonization of Chorales, in the Style of J. S. Bach,”Technical Report, TR 86-09, Dept. of Computer Science, S. U. N. Y., Buffalo, March, 1986.)

    Google Scholar 

  8. Ebcioĝlu, K., “An Efficient Logic Programming Language and its Application to Music,”Proc. 4th ICLP, May, 1987.

  9. Ebicoĝlu, K., “A Compilation Technique for Software Pipelining of Loops with Conditional Jumps,”Proc. 20th Annual Workshop on Microprogramming (MICRO-20), December, 1987.

  10. Ebcioĝlu, K., “Some Design Ideas for a VLIW Architecture for Sequential-Natured Software,” inParallel Processing (Proc. IFIP WG 10.3 Working Conference on Parallel Processing), (Cosnard, M. et al. eds.), North Holland, April, 1988.

  11. Ebcioĝlu, K., “An Expert Expert System for Harmonizing Four-part Chorales,”Computer Music Journal,Vol. 12,No. 3, Fall, 1988.

  12. Ebcioĝlu, K. and Nakatani, T., “A New Compilation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture,” inProc. Second Workshop on Programming Languages and Compilers for Parallel Computing, Univ. of Illinois, Urbana-Champaign, Aug., 1989.

    Google Scholar 

  13. Ebcioĝlu, K., “An Expert System for Harmonizing Chorales in the Style of J. S. Bach,”Special Issue of the Journal of Logic Programming on Applications of Logic Programming, to appear, Jan.-March, 1990.

  14. Ellis, J. R.,Bulldog: A Compiler for VLIW Architectures, MIT Press, 1986.

  15. Fagin, B. and Dobry, T., “The Berkeley PLM Instruction Set: An Instruction Set for Prolog,”Report, No. UCB/CSD 86/257, Computer Science Division (EECS), University of California, Berkeley, September, 1985.

    Google Scholar 

  16. Fisher, J. A., “The VLIW Machine: A Multiprocessor for Compiling Scientific Code,”COMPUTER 17 (7), July, 1984, pp. 45–53.

    Article  Google Scholar 

  17. Floyd, R., “Nondeterministic Algorithms,”Journal of the Association for Computing Machinery,Vol. 14,No. 4, October, 1967.

  18. Forgy, C. and McDermott, J., “OPS: A Domain Independent Production System Language,”Proceedings of the fifth International Joint Conference in Artificial Intelligence, 1977.

  19. Harel, D., “First Order Dynamic Logic,”Lecture Notes in Computer Science (Goos and Hartmanis eds.), Spring-Verlag, 1979.

  20. IBM, “3090 Processor Complex Functional Characteristics,”Publication, Number SA 22-7121-5, IBM Corp., Poughkeepsee, NY, 1987.

    Google Scholar 

  21. Kale, L. V., “The REDUCE-OR Process Model for Parallel Evaluation of Logic Programs,”Proc. 4th International Conference on Logic Programming, 1987.

  22. Kurokawa, T., Tamura, N., Asakawa, Y. and Komatsu, H., “A Very Fast Prolong Compiler on Multiple Architectures,”Proc. FJCC, 1986.

  23. Maruyama, T., Hirata, K., Tanaka, H. and Moto-Oka, T., “A Note on the Elementary Execution Unit in a Parallel Inference Machine,”Proc. 4th Conference on Logic Programming, Tokyo, 1985.

  24. Nicolau, A., “Percolation Scheduling: A Parallel Compilation Technique,”TR 85-678, Dept. of Computer Science, Cornell University, May, 1985.

  25. Onai, R., Shimizu, H., Masuda, K., Matsumoto, A. and Aso, M., “Architecture and Evaluation of a Reduction-based Parallel Inference Machine: PIM-R,”Proc. 4th Conference on Logic Programming, Tokyo, 1985.

  26. Robinson, J. A., “A Machine Oriented Logic Based on the Resolution Principle,”Journal of the Association for Computing Machinery 12, 1965.

  27. Robinson, J. A., “A Machine Oriented Logic Based on the Resolution Principle,”Journal of the Association for Computing Machinery 12, 1965.

  28. Smith, D. C. and Enea, H. J., “Backtracking in Mlisp2,”Proceedings of the third International Joint Conference in Artificial Intelligence, 1973.

  29. Turk, A. W., “Compiler Optimizations for the WAM”Proc. 3rd ICLP, 1986.

  30. Ueda, K., “Guarded Horn Clauses,”ICOT, Technical Report, TR-103, Tokyo, 1985.

  31. Warren, S. H., Auslander, M. A., Chaitin, G. J., Chibib, A. C., Hopkins, M. E. and MacKay, A. L., “Final Code Generation in the PL. 8 Compiler,”Report, No. RC 11974, IBM T. J. Watson Research Center, 1986.

Download references

Author information

Authors and Affiliations

Authors

About this article

Cite this article

Ebcioĝlu, K., Kumar, M. A wide instruction word architecture for parallel execution of logic programs coded in BSL. NGCO 7, 219–242 (1990). https://doi.org/10.1007/BF03037207

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF03037207

Keywords

Navigation