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Towards a pipelined Prolog processor

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Abstract

This paper describes the design of a Prolog machine architecture and organization. Our objective was to determine the maximum performance attainable by a sequential Prolog machine for “reasonable” cost. The paper compares the organization to both general purpose micro-coded machines and reduced instruction set machines. Hand timings indicate a peak performance rate of 450 K LIPS (logical inferences per second) is well within current technology limitations and 1 M LIPS is potentially feasible.

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References

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Adapted from the paper “TOWARDS A PIPELINED PROLOG PROCESSOR” by Evan Tick and David H.D. Warren appearing in 1984 INTERNATIONAL SYMPOSIUM ON LOGIC PROGRAMMING, February 6–9, 1984, Atlantic City, NJ, pp. 29–40. Copyright © 1984 IEEE.

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Tick, E., Warren, D.H.D. Towards a pipelined Prolog processor. New Gener Comput 2, 323–345 (1984). https://doi.org/10.1007/BF03037325

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  • DOI: https://doi.org/10.1007/BF03037325

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