Abstract
Techniques of hierarchical specification and verification of hardware with temporal logic and Prolog are presented by example. Both hardware designs in gates and state-diagrams are translated into a relation between the present and the next state, which is represented in Prolog.1) Specifications are constructed by temporal logic that can express state sequences (e.g. timing diagrams) easily and also are translated into a relation between the present and the next state in Prolog.
The verification method is based upon the temporal logic decision procedure in Ref. 2) and, referring to the relation tables between the present state and the next state, the verifier can reason in both directions—forward and backward in temporal sequences. Prolog has very powerful pattern matching, and its automatic backtracking capabilities facilitate easy-to-write verifier programs.
It is concluded that a total verification system handling various design levels can be constructed with temporal logic and Prolog.
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Fujita, M., Tanaka, H. & Moto-Oka, T. Temporal logic based hardware description and its verification with Prolog. New Gener Comput 1, 195–203 (1983). https://doi.org/10.1007/BF03037426
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DOI: https://doi.org/10.1007/BF03037426