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Power consumption reduction in systems on Chip (SoCs)

Réduction de la Consommation de Puissance dans les Systèmes sur Puces

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Abstract

Systems on Chip are becoming extremely complex integrated circuits, containing tens or hundreds of analog,rf and digital blocks. For most applications, they have to present extremely low power consumption. It is the case, for instance, in ad hoc networks for which 100 or 1000 SoC nodes have to sense their environment, do some processing and send by radio some information to adjacent nodes in a multi-hop fashion to reach finally a base station. The design of such SoC nodes, to achieve the required extremely low power consumption, has to performed first at the system level, including low power communication protocols and data routing through the network, node wake-up strategies, low-power software and operating systems, innovative solutions for the sensor part, flexible or reconfigurable and very low power digital processing, low-power networks on chip for the communication between embedded processors and memories, as well as low powerrf front-ends. In addition, due to the impressive technology pace, new problems have to be solved for the design of SoCs, such as the interconnect delays, reliability and the dramatic increase of the static power. Some techniques, considered as the most efficient, of dynamic as well as static power reduction are described. It is however shown that the design of SoCs in 130 nm and below will impact dramatically the design methodologies, mainly due the static power increase. Finally, if today most SoCs are powered by batteries, alternative sources of energy are reviewed.

Résumé

Les Systèmes sur Puce deviennent des circuits intégrés extrêmement complexes, contenant des dizaines ou des centaines de blocs analogiques, radio et numériques. Pour la majorité des applications, ils doivent présenter une consommation de puissance électrique extrêmement faible. C’est le cas, par exemple, des réseaux d’objets communicants, dans lesquels une centaine ou un millier d’objets doivent sonder leur environnement, effectuer un traitement numérique et envoyer par radio des informations à des objets voisins en plusieurs sauts vers une station de base. La conception des ces systèmes sur puce, pour parvenir à des consommations très basses, doit se faire premièrement au niveau système, considérant des protocoles de communication basse puissance et le routage des informations dans le réseau, des stratégies de réveil des objets communicants, des logiciels et des systèmes d’exploitation basse puissance, des solutions innovatrices pour les capteurs, des processeurs de traitement numérique à la fois flexibles, reconfigurables et basse puissance, des réseaux de communication entre processeurs et mémoires embarqués, ainsi que des têtes radiofréquences à très basse puissance. De plus, les progrès technologiques impressionnants ont pour résultat de poser des nouveaux problèmes dans la conception des systèmes sur puce, comme les délais des interconnexions, la fiabilité et l’accroissement significatif de la puissance statique. Quelques techniques parmi les plus efficaces de réduction des puissances dynamique et statique sont présentées. Cependant, la conception des systèmes sur puce dans des technologies de 130 nanomètres et plus bas va remettre en cause les méthodes de conception habituelles, essentiellement à la suite de l’accroissement significatif de la puissance statique. Finalement, si la majorité des systèmes sur puce d’aujourd’hui sont alimentés par des batteries, des sources d’énergies alternatives sont décrites.

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References

  1. Akyildiz (I. F.),Su (W.),Sankarasubramaniam (Y.),Cayirci (E.), «Wireless Sensor Network: A Survey»,Computer Networks38, 2002, pp. 394–422, Elsevier.

    Article  Google Scholar 

  2. Agarwala (P.), “Energy efficient protocols for wireless systems”,Proc. 9thieee Intl. Symp. on Personal, Indoor and Mobile Radio Communications, pp. 564–569.

  3. Rabaey (J.), “Low-Energy Wireless System Design — Looking beyond the next generation”,Tutorial atftfc’2001, third French Workshop in Low-Voltage Low-Power, Paris, June 1, 2001, France.

  4. Maleki (M.),Dantu (K.),Pedram (M.), “Power-aware Source Routing Protocol for Mobile Ad Hoc Networks”,Proc.islped’02, Monterey, CA, August 12–14, 2002, pp. 72–75.

  5. Ruedi (P.-F.),Heim (P.),Kaess (F.),Grenet (E.),Heitger (F.),Burgi (P.-Y.),Gyger (S.),Nussbaum (P.), “A 128×128 pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction,”ieee J. Solid-State Circuits,38, No. 12, pp. 2325–2333, 2003.

    Article  Google Scholar 

  6. Melly (T.),Porret (A.S.),Enz (Ch.),Vittoz (E.), «An Ultralow-Poweruhf Transceiver Integrated in a Standard Digitalcmos Process: Transmitter,ieee jssc,36, No 3, March 2001, pp. 467–472.

    Google Scholar 

  7. Rampogna (F.)et al. “macgic, A low power, re-configurabledsp”, Chapter 21, in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  8. Dey (S.),Raghunathan (A.), “Low-Power Mobile Wireless Communication System Design: Protocols, Architectures and Design Methodologies”,Tutorial atdate 2002.

  9. Benini (L.),Tao Ye (T.),De Micheli (G.), “Networks on Chips — Energy-efficient Design of SoC Interconnect”, Chapter 30 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  10. Svensson (C.), “Low-Power and Low-Voltage Communication for SoCs”, Chapter 14 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  11. O’connor (I.),Gaffiot (F.), “Advanced Research in On-Chip Optical Interconnects”, Chapter 5 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  12. Semiconductor Industry Association (sia),The International Technology Roadmap for Semiconductors, 2001

  13. Belleville (M.),Faynot (O.), “Evolution of Deep Submicron Bulk andsoi Technologies”, Chapter 2 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  14. Lundstrom (M.), “Microelectronics, Nanoelectronics and the Future of Electronics”, Chapter 4 in “Low Power Electronics Design”,CRC Press, edited by C. Piguet, will be published in 2004.

  15. Piguet (C.), “Low-Power Issues for SoCs”,Proc. DATE 2001, Münich, 13–16 March 2001, pp. 488–490.

  16. Moore (S.),Anderson (R.),Cunningham (P.),Mullins (R.),Taylor (G.), “Improving Smart Card security using self-timed circuits”,Proc. of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Manchester, April 2002, pp. 211–18.

  17. Hai Liet al, “dcg: Deterministic Clock Gating for Low-Power Microprocessor Design”,ieee Trans.vlsi Design, Special Issue in Low-Power, 2003

  18. Arm (C.),Masgonty (J-M.),Piguet (C.), “Double-Latch Clocking Scheme for Low-Powerip. Cores”,Type="Italic"> patmos 2000, Goettingen, Germany, September 13–15, 2000.

  19. Chandrakasan (A. P.),Sheng (S.),Brodersen (R. W.), “Low-Powercmos Digital Design”,ieee J. of Solid-State Circuits,27, no 4, April 1992, pp. 473–484.

    Article  Google Scholar 

  20. Piguet (C.), “Low-Power and Low-Voltagecmos Digital Digital Design”,Elsevier Microelectronic Engineering 39, 1997, pp. 179–208.

    Article  Google Scholar 

  21. Pardoen (M.),Gerrits (J.),Von Kaenel (V.), “A 0.9 V — 1.2 mA 200 MHzbicmos Single Chip Narrow Bandfm Receiver”,Proc.isscc’96,39, 1996, pp-348–349.

    Google Scholar 

  22. Sinha (A.),Chandrakasan (A. P.), “Dynamic Power Management in Wireless Sensor Networks”,ieee Design and Test of Computers, March–April 2001, pp. 62–74.

  23. Ishihara (F.)et al. “Level Conversion for Dual-Supply Systems”,ieee Trans.vlsi Design, Special Issue in Low-Power, 2003.

  24. Masgonty (J-M.),Cserveny (S.),Arm (C.),Pfister (P-D.),Piguet (C.), “Low-Power Low-Voltage Standard Library Cells with a Limited Number of Cells”,patmos 2001, 26–28 September 2001, Yverdon, Switzerland.

  25. Sakurai (T.), “Perspectives on Power-Aware Electronics”, Plenary Talk 1.2,Proc.isscc 2003, San-Francisco, CA, Feb. 9–13, 2003, pp. 26–29.

  26. Kosonocky (S. V.),Immediato (M.),Cottrell (P.),Hook (T.),Mann (R.),Brown (J.), “Enhanced Multi-Threshold (mtcmos) Circuits Using Variable Well Bias”,Proc.islped’01, Huntington Beach,ca, August 6–7, 2001, pp. 165–169.

  27. Narendra (S.),Borkar (S.),De (V.),Antoniadis (D.),Chandrakasan (A.), “Scaling of Stack Effect and its Application for Leakage Reduction”,Proc.islped’01, Huntington Beach,ca; August 6–7, 2001, pp. 195–200.

  28. Assaderaghi (F.),Sinitsky (D.),Parke (S.),Bokor (J.),Ko (P.K.),Hu (C.) “A Dynamic Threshold Voltage (dtmos) for ultra-low Voltage Operation”,ieee iedm Tech. Dig., Conf. 33.1.1, 1994, pp. 809–812.

  29. Enomoto (T.),Oka (Y.),Shikano (H.),Harada (T.), “A Self-Controllable-Voltage-Level (svl) Circuit for Low-Power High-Speedcmos Circuits”,Proceedingsesscirc 2002, pp. 411–414.

  30. Cserveny (S.),Masgonty (J-M.),Piguet (C.), “Stand-by Power Reduction for Storage Circuits”,Proc.patmos 2003, Torino, Italy, 10–12 September 2003.

  31. Heer (C.), “Designing low-power circuits: an industrial point of view”,Proc.patmos 2001, Yverdon, Switzerland, September 26–28, 2001

  32. Piguet (C.)et al. “Techniques de circuits et méthodes de conception pour réduire la consommation statique dans les technologies profondément submicroniques”,Proc.ftfc’03, Paris, May 15–16, 2003, pp. 21–29.

  33. Ohtsuka (H.)et al. « Preparation and the cell performance of rechargeable thin film lithium batteries »,ntt in Micromechanics,43, no 2, June 1999.

  34. Bertozzi (D.),Benini (L.), “Battery Lifetime Optimization for Energy-Aware Circuits”, Chapter 43 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  35. Benini (L.),Castelli (G.),Macii (A.), “Battery-Driven Dynamic Power Management”,ieee Design and Test of Computers, March–April 2001,18, no 2, pp. 53–60.

    Article  Google Scholar 

  36. Benini (L.),Castelli (G.),Macii (A.),Macii (E.),Poncino (M.),Scarsi (R.) “Extending Lifetime of Portable Systems by Battery Scheduling”,Proc.date 2001, pp. 197–203.

  37. Benini (L.),Castelli (G.),Macii (A.),Macii (E.),Scarsi (R.), “Battery-Driven Dynamic Power Management of Portable Systems”,Proc. 13th Int. Symp. on System Synthesis, Madrid, Spain, Sept. 20–22, 2000, pp. 25–30.

  38. Benini (L.)et al. “Discrete Time Battery Models for System-Level Low-Power Design”,ieee Trans. onvlsi Systems,9, no 5, October 2001, pp. 630–640.

    Article  MathSciNet  Google Scholar 

  39. Bloch (D.), “Miniature Fuel Cells for Portable Applications, Chapter 44 in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

  40. Kanesaka (T.), “Development of a Thermal Energy Watch”,Proc. 64th Conference on Chronometry (Société Suisse de Chronométrie), Le Sentier, Switzerland, Sept. 30–Oct. 1, 1999, pp. 19–22.

  41. Douseki (T.)et al. “A Batteryless Wireless System Uses Ambient Heat with a Reversible-Power-Source Compatiblecmos/soi dc-dc converter”,Proc.isscc2003, Conf. 22.2, pp. 388–389.

  42. Jung (S.),Lauterbach (C.),Strasser (M.),Weber (W.), “Enabling Technologies for Disappearing Electronics in Smart Textiles”,Proc.isscc 2003, Conf. 22.1, pp. 386–387.

  43. Schmidt (M.), “Portablemems Power Sources”,Proc.isscc 2003, Conf. 22.5, pp. 394–395.

  44. Starner (T.), “Human-powered wearable computing”,ibm Systems Journal,35, Nos 3&4, 1996, pp. 618–629.

    Article  Google Scholar 

  45. Starner (T.), “Human Powered Sources of Energy”, Chapter in in “Low Power Electronics Design”,crc Press, edited by C. Piguet, will be published in 2004.

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  1. CSEM and LAP-EPFL; CSEM, Jaquet-Drotz 1, 2000, Neuchâtel, Suisse

    Christian Piguet

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Piguet, C. Power consumption reduction in systems on Chip (SoCs). Ann. Télécommun. 59, 884–902 (2004). https://doi.org/10.1007/BF03180026

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