Abstract
Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that follow the rates predicted in Moore’s law. The tradeoffs in area, speed and power, allowed by theCmos technology, and its capacity to integrate analog, digital and mixed components, are key features to its dissemination in the telecommunications field. In fact, the progress of theCmos technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. As integrated circuits evolve, they approach some limits that make further improvements more difficult and even unpredictable. With deep-submicron structures, the yield of manufacturing processes is one of the main challenges of the semiconductor industry, with negative impacts on time-to-market and profitability. With reduced voltages and increased speed and density, the reliability of deep-submicron circuits is another concern for designers, since noise immunity is reduced and thermal noise effects show-up. In this paper we present an overview of the issues related with the scaling of integrated circuits into nanometer technologies, detailing the yield and reliability problems. We present the state of the art in proposed solutions and alternatives that can improve the chances of a large utilization of these nanotechnologies.
Résumé
Les circuits intégrés ont connu une évolution constante au cours des dernières décennies, avec des améliorations en densité et en vitesse qui suivent les variations prévues par la loi de Moore. Les possibilités offertes par la technologieCmos d’échanges entre surface, vitesse et puissance ainsi que d’intégration de composants analogiques, numériques et mixtes sont la raison principale de la large diffusion de cette technologie dans le domaine des télécommunications. En effet, les progrès de la technologieCmos ont contribué à l’évolution de ce domaine, par l’intégration de fonctions de plus en plus complexes, diverses et demandeuses de puissance de calcul. Néanmoins, plus les circuits intégrés évoluent, plus ceux-ci approchent certaines limites rendant de nouvelles améliorations plus difficiles voire impossibles ou tout au moins imprévisibles. Le rendement des procédés de fabrication employant des structures fortement submicroniques est l’un des défis majeurs de l’industrie des semiconducteurs, du fait de son impact négatif sur le délai de mise sur le marché et la rentabilité. Par ailleurs, la réduction des tensions, l’augmentation des fréquences et l’accroissement de la densité d’intégration font de la fiabilité des circuits fortement submicroniques un autre défi pour les concepteurs, puisque l’immunité au bruit est de ce fait réduite et que les effets du bruit thermique augmentent. Dans cet article, nous établissons un panorama des questions liées à l’arrivée des circuits intégrés en technologies nanométriques en nous intéressant tout particulièrement aux problèmes de rendement et de fiabilité. Nous présentons l’état de l’art des solutions proposées et proposons quelques pistes alternatives qui permettraient de lever les verrous à l’utilisation plus large de ces technologies.
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Teixeira Franco, D., Naviner, JF. & Naviner, L. Yield and reliability issues in nanoelectronic technologies. Ann. Télécommun. 61, 1422–1457 (2006). https://doi.org/10.1007/BF03219903
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DOI: https://doi.org/10.1007/BF03219903
Key words
- Nanotechnology
- Cmos
- Microelectronic fabrication
- Semiconductor technology
- Integrated circuit
- Yield
- Reliability
- Logic circuit
- Fault tolerance system
- System design
- Reconfigurable circuit
- State of the art