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Global register allocation based on graph fusion

  • Instruction Scheduling and Register Allocation
  • Conference paper
  • First Online:
Languages and Compilers for Parallel Computing (LCPC 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1239))

Abstract

A register allocator must effectively deal with three issues: live range splitting, live range spilling, and register assignment. This paper presents a new coloring-based global register allocation algorithm that addresses all three issues in an integrated way: the algorithm starts with an interference graph for each region of the program, where a region can be a basic block, a loop nest, a superblock, a trace, or another combination of basic blocks. Region formation is orthogonal to register allocation in this framework. Then the interference graphs for adjacent regions are fused to build up the complete interference graph. The algorithm delays decisions on splitting, spilling, and register assignment, and therefore, the register allocation may be better than what is obtained by a Chatin-style allocator. This algorithm uses execution probabilities, derived from either profiles or static estimates, to guide fusing interference graphs, allowing an easy integration of this register allocator into a region-based compiler.

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References

  1. D. Bernstein, D. Q. Goldin, M. C. Golumbic, H. Krawczyk, Y. Mansour, I. Nahshon, and R. Y. Pinter. Spill code minimization techniques for optimizing compilers. In Proc. ACM SIGPLAN '89 Conf. on Prog. Language Design and Implementation, pages 258–263. ACM, July 1989.

    Google Scholar 

  2. P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

    Google Scholar 

  3. P. Briggs, K. D. Cooper, K. Kennedy, and L. Torczon. Coloring heuristics for register allocation. In Proc. ACM SIGPLAN'89 Conf. on Prog. Language Design and Implementation, pages 275–284. ACM, July 1989.

    Google Scholar 

  4. D. Callahan and B. Koblenz. Register allocation via hierarchical graph coloring. In Proc. ACM SIGPLAN'91 Conf. on Prog. Language Design and Implementation, pages 192–203, Toronto, June 1991. ACM.

    Google Scholar 

  5. G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, M. E. Hopkins, and P. W. Markstein. Register allocation by coloring. Research Report 8395, IBM Watson Research Center, 1981.

    Google Scholar 

  6. P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Warter, and W. W. Hwu. Impact: An architectural framework for multiple-instruction-issue processors. In Proc. 18th Intl. Symp. on Computer Architecture, pages 266–275. ACM/IEEE, May 1991.

    Google Scholar 

  7. F. C. Chow and J. L. Hennessy. A priority-based coloring approach to register allocation. ACM Trans. on Prog. Lang. Syst., 12:501–535, Oct. 1990.

    Article  Google Scholar 

  8. J. A. Fisher and S. M. Freudenberger. Predicting conditional branch direction from previous runs of a program. In Proc. Fifth Intl. Conf. on Architectural Support for Prog. Languages and Operating Systems (ASPLOS V), pages 85–97. ACM, October 1992.

    Google Scholar 

  9. S. Freudenberger and J. Ruttenberg. Phase ordering of register allocation and instruction scheduling. In R. Giegerich and S. L. Graham, editors, Code Generation — Concepts, Tools, Techniques, pages 146–170. Springer Verlag, 1992.

    Google Scholar 

  10. R. Hank, W. Hwu, and B. Rau. Region-based compilation: An introduction and motivation. In Proc. 28th Annual ACM/IEEE Intl. Symp. on Microarchitecture, pages 158–168, Ann Arbor, Nov 1995. ACM/IEEE.

    Google Scholar 

  11. W. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. O. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery. The superblock: An effective technique for vliw and superscalar compilation. Journal of Supercomputing, 7(1,2):229–248, March 1993.

    Article  Google Scholar 

  12. M. S. Johnson and T. C. Miller. Effectiveness of a machine-level global optimizer. In Proc. ACM SIGPLAN '86 Symp. on Compler Construction, pages 99–108. ACM, July 1986.

    Google Scholar 

  13. P. Kolte and M. J. Harrold. Load/store range analysis for global register allocation. In Proc. ACM SIGPLAN '93 Conf. on Prog. Language Design and Implementation, pages 268–277. ACM, June 1993.

    Google Scholar 

  14. P. G. Lowney, S. M. Freudenberger, T. J. Karzes, W. D. Lichtenstein, R. P. Nix, J. O'Donnell, and J. C. Ruttenberg. The multiflow trace scheduling compiler. Journal of Supercomputing,7(1,2):51–142, March 1993.

    Article  Google Scholar 

  15. C. Norris and L. L. Pollock. Register allocation over the program dependence graph. In Proc. ACM SIGPLAN '94 Conf. on Prog. Language Design and Implementation, pages 266–277. ACM, June 1994.

    Google Scholar 

  16. D. Wall. Predicting program behavior using real or estimated profiles. In Proc. ACM SIGPLAN '91 Conf. on Compiler Construction, pages 59–70. ACM, June 1991.

    Google Scholar 

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Author information

Authors and Affiliations

  1. School of Computer Science, Carnegie Mellon University, 15213, Pittsburgh, PA

    Thomas Gross & Ali-Reza Adl-Tabatabai

  2. Institut für Computer Systeme, ETH Zurich, 8092, Zürich, CH

    Thomas Gross

  3. ECE Department, Carnegie Mellon University, 15213, Pittsburgh, PA

    Guei-Yuan Lueh

Authors
  1. Guei-Yuan Lueh
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  2. Thomas Gross
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  3. Ali-Reza Adl-Tabatabai
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Editor information

David Sehr Utpal Banerjee David Gelernter Alex Nicolau David Padua

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© 1997 Springer-Verlag Berlin Heidelberg

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Lueh, GY., Gross, T., Adl-Tabatabai, AR. (1997). Global register allocation based on graph fusion. In: Sehr, D., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1996. Lecture Notes in Computer Science, vol 1239. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0017257

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  • DOI: https://doi.org/10.1007/BFb0017257

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63091-3

  • Online ISBN: 978-3-540-69128-0

  • eBook Packages: Springer Book Archive

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