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Automatic parallelization for non-cache coherent multiprocessors

  • Parallelizing Compilers
  • Conference paper
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Languages and Compilers for Parallel Computing (LCPC 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1239))

Abstract

Although much work has been done on parallelizing compilers for cache coherent shared memory multiprocessors and message-passing multiprocessors, there is relatively little research on parallelizing compilers for non-cache coherent multiprocessors with global address space. In this paper, we present a preliminary study on automatic parallelization for the Cray T3D, a commercial scalable machine with a global memory space and non-coherent caches.

The research described is supported by Army contract #DABT63-95-C-0097. This work is not necessarily representative of the positions or policies of the Army or the Government.

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 West Springfield Avenue, 61801, Urbana, IL, USA

    Yunheung Paek & David A. Padua

Authors
  1. Yunheung Paek
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  2. David A. Padua
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Editor information

David Sehr Utpal Banerjee David Gelernter Alex Nicolau David Padua

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© 1997 Springer-Verlag Berlin Heidelberg

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Paek, Y., Padua, D.A. (1997). Automatic parallelization for non-cache coherent multiprocessors. In: Sehr, D., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1996. Lecture Notes in Computer Science, vol 1239. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0017258

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  • DOI: https://doi.org/10.1007/BFb0017258

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63091-3

  • Online ISBN: 978-3-540-69128-0

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