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Compiler support for maintaining cache coherence using data prefetching (extended abstract)

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Languages and Compilers for Parallel Computing (LCPC 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1239))

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References

  1. L. Choi. Hardware and Compiler Support for Cache Coherence in Large-Scale Multiprocessors. PhD thesis, Center for Supercomputing R & D, UIUC, March 1996.

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  2. L. Choi, H.-B. Lim, and P.-C. Yew. Multiprocessor cache coherence: A compiler-directed approach. To appear in IEEE Parallel & Distributed Tech., Winter 1996.

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  3. E. Gornish. Compile time analysis for data prefetching. Master's thesis, Center for Supercomputing R & D, UIUC, December 1989.

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  4. T. Mowry. Tolerating Latency Through Software-Controlled Data Prefetching. PhD thesis, Dept. of Elect. Eng., Stanford University, March 1994.

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Author information

Authors and Affiliations

  1. Center for Supercomputing R & D, Univ. of Illinois, 61801, Urbana, IL

    Hock-Beng Lim

  2. Microprocessor Group, Intel Corporation, 95095, Santa Clara, CA

    Lynn Choi

  3. Dept. of Computer Science, Univ. of Minnesota, 55455, Minneapolis, MN

    Pen-Chung Yew

Authors
  1. Hock-Beng Lim
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  2. Lynn Choi
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  3. Pen-Chung Yew
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Editor information

David Sehr Utpal Banerjee David Gelernter Alex Nicolau David Padua

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© 1997 Springer-Verlag Berlin Heidelberg

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Lim, HB., Choi, L., Yew, PC. (1997). Compiler support for maintaining cache coherence using data prefetching (extended abstract). In: Sehr, D., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1996. Lecture Notes in Computer Science, vol 1239. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0017278

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  • DOI: https://doi.org/10.1007/BFb0017278

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63091-3

  • Online ISBN: 978-3-540-69128-0

  • eBook Packages: Springer Book Archive

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