Abstract
This paper presents a multithreaded superscalar processor that permits several threads to issue instructions to the execution units of a wide superscalar processor in a single cycle. Instructions can simultaneously be issued from up to 8 threads with a total issue bandwidth of 8 instructions per cycle. Our results show that the 8-threaded 8-issue processor reaches a throughput of 4.2 instructions per cycle.
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References
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© 1996 Springer-Verlag Berlin Heidelberg
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Sigmund, U., Ungerer, T. (1996). Identifying bottlenecks in a multithreaded superscalar microprocessor. In: Bougé, L., Fraigniaud, P., Mignotte, A., Robert, Y. (eds) Euro-Par'96 Parallel Processing. Euro-Par 1996. Lecture Notes in Computer Science, vol 1124. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0024779
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DOI: https://doi.org/10.1007/BFb0024779
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