VLIW compilation techniques for superscalar architectures

Abstract

Efficient use of multiple functional units in superscalar processors requires instruction level parallelism to be detected and exploited. Thus special hardware in the form of dispatch units is used to uncover scheduling opportunities within an instruction window at run-time. Using the superscalar PowerPC 604 as an example we show that such processors still benefit from more broadly scoped scheduling at compile time. In our approach we reuse an existing retargetable VLIW compiler environment by instantiating it for a VLIW processor whose resources and instruction timings resemble those of the PowerPC.

This paper presents the transformation of the resulting horizontal VLIW code into vertical superscalar code and gives measurements showing the improvements gained from compile time scheduling.

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