Abstract
A set of algebraic tools are presented to model superscalar processors, where instructions may be executed in parallel, or out of program order. This has implications for the representation of timing abstraction, the relationship between time at different levels of abstraction, and the concept of the correctness of one representation with respect to another. We illustrate our tools with a simple, superscalar example, and present a one-step theorem for simplifying the formal verification of superscalar microprocessors.
Supported by EPSRC grant number 94007861.
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Fox, A.C.J., Harman, N.A. (1996). An algebraic model of correctness for superscalar microprocessors. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031820
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DOI: https://doi.org/10.1007/BFb0031820
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