Abstract
A new parallel MIMD architecture is described each node of which is tightly coupled to a global programmable logic layer. This layer gives local acceleration to the node processors by massive micro-grain parallelism. It also provides fast computation services to distributed algorithms by synthesis of global dedicated units operating directly on node operands. As a result, fine approximations of global states become transparently visible in each node, in contrast with usual difficulties and delays in sharing and computing control data.
This point is emphasized by the description of two parallel virtual time mechanisms. The first study involves increasing virtual clocks, and the second one takes into account time counter overflows in a time warp environment. Implementations are based on global systolic networks, fed by the array of local operands and controlled by a small automaton. Thus, global states are handled for each cycle of the mechanism, and results become visible after one pipeline delay with no cost for the accelerated parallel machine.
To summarize general characteristics of this architecture are: general purpose, reconfigurability, cheapness, extensibility.
This work is supported by Région Bretagne and Municipalité de Brest. The Armen machine implementation is supported by ANVAR.
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References
P.Bertin, D.Roncin, J.Vuillemin, “Introduction to programmable active memories”, in Systolic Array Processors, Prentice Hall, pp. 301, 1989.
S. Bellenot, “Global Virtual Time Algorithms”, in Proc. of the SCS multiconference on Distributed Simulation, San Diego, Californie, pp. 122, 19 January 1990.
C.Buzzell, M.J.Robb, R.Fujimoto, “Modular VME rollback approach for Time Warp”, in Proc. of the SCS multiconference on Distributed Simulation, San Diego, Californie, pp. 153, 19 January 1990.
A.Gottlieb and al., “The NYU Ultracomputer — Designing an MIMD shared memory parallel computer”, in Proc. International Conference on Computer Architecture, ACM, pp. 175. 1982.
D.Jefferson, H.Sowizral, “Fast concurrent simulation using the time warp mechanism”, in Proc. of the SCS Conference on Distributed Simulation, San Diego, pp. 63–69, Jan. 1985.
D.Jefferson, “Virtual Time”, Transactions on Programming, Languages and Systems, ACM, vol. 7, no. 3, pp. 404, 1985.
R.Fujimoto, J-J.Tsai, G.Gopalakrishnan, “Design and performance of special purpose hardware for Time Warp”, in Proc. of International Symposium on Computer Architecture, IEEE, pp. 401, 1988.
T.Kean, J.Gray, “Configurable hardware: two case studies of micro-grain calculation”, in Systolic Array Processors, Prentice Hall, pp. 310, 1989.
B.W. Lampson, K.A.Pier, “A Processor for a High-Performance Personal Computer”, in Proc. of Computer Architecture Symposium, IEEE-ACM, pp. 146, 1980.
H.T.Kung, “Why systolic architectures?”, IEEE Computer, vol. 15, no. 1, pp. 37, 1982.
H.T.Kung, “Network-based multicomputers: redefining high performance computing in the 1990s”, in Proc. of the Decennial Caltech Conference on VLSI, The MIT Press, pp. 49, 1989.
L.Lamport, “Time, Clocks, and the Ordering of Events in a Distributed System”, Communications of the ACM, vol. 21, no. 7, pp. 558, 1978.
J.Misra, “Distributed Discrete Event Simulation”, Computing Surveys, vol. 18, no. 1, pp. 39, March 1986.
B.Pottier, D.Lavenier, “High rate sigma filtering, feasibility studies on processor networks”, in Proc. of IFIP Workshop “Parallel architectures on Silicon”, INP Grenoble, pp. 182, 1989.
B.Pottier, “Machines parallèles à accélérateurs reconfigurables”, Thèse de l’Université de Rennes 1, Dec. 1990.
M. Raynal, A distributed algorithm to prevent mutual drift between N logical clocks, Information Processing Letters, vol. 24, no. 3, pp. 199–202, Feb 1987.
B. Samadi, “Distributed Simulation, Algorithms and Performance Analysis”, PhD. Num 8513157, University of California, Los Angeles, pp. 35–64, 1985.
J.Viitanen, T.Kean, “Image pattern recognition using configurable Logic Cell Arrays”, in Proc. of Computer Graphic International ’89, Springer-Verlag, pp. 355, 1989.
Xilinx, The Programmable Gate Array Data Book, Xilinx, San Jose, 1990.
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Filloque, J.M., Gautrin, E., Pottier, B. (1991). Efficient Global Computations on a Processor Network with Programmable Logic. In: Aarts, E.H.L., van Leeuwen, J., Rem, M. (eds) Parle ’91 Parallel Architectures and Languages Europe. Lecture Notes in Computer Science, vol 505. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-25209-3_6
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