Skip to main content

An automatic speed-up of random access machines with powerful arithmetic instructions

  • Contributed Papers
  • Conference paper
  • First Online:
STACS 88 (STACS 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 294))

Included in the following conference series:

  • 150 Accesses

Abstract

Speeding up automatically means to find a parallel algorithm for an arbitrary sequential one, so that the time for designing this parallel algorithm plus its runtime is considerably lower than the time sequentially used. Here we consider sequential and parallel random access machines (RAMs, PRAMs) with arithmetic instructions {+, −, *}. RAMs work on integer inputs and use direct and a restricted form of indirect addressing, only.

We extend the result of Meyer auf der Heide ([MEYE86]) to RAMs which can also multiply. We use techniques for fast parallel computation of polynomials due to Valiant, Skyum, Berkowitz and Rackoff ([VSBR83]). In order to apply this we have to make their simulation uniform. This result, interesting in itself, is based on an efficient parallelization of straight-line programs with operations {+,max}.

With a PRAM with a processors we gain a speed up factor of \(\frac{{(log log q)^2 + log log q \cdot log D}}{{log q}}\)for any uniform RAM P, where D denotes the formal degree of the polynomials computed by P.

Work supported by the Deutsche Forschungsgemeinschaft, grants No. ME 872/1-1

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Kucera, L.: Parallel Computation and Conflicts in Memory Access, Information Processing Letters 14(2), 1982, pp. 93–96

    Google Scholar 

  2. Meyer auf der Heide, F.: Lower Bounds for Solving Linear Diophantine Equations on several parallel computational models, Information and Control, Vol. 67, Nos. 1–3, 1985, pp. 195–211

    Google Scholar 

  3. Meyer auf der Heide, F.: Speeding up Random Access Machines by Few Processors, Proc. 3rd STACS, 1986, pp. 142–152

    Google Scholar 

  4. Miller, G.L., Ramachandran, V., Kaltofen, E.: Efficient Parallel Evaluation of Straight-line Code and Arithmetic Circuits, VLSI Algorithms and Architectures, Proc. of the Aegean Workshop on Computing, Loutraki, 1986, pp. 236–245

    Google Scholar 

  5. Valiant, L.G.: Parallelism in Comparison Problems, SIAM J. Computing, No. 3, 1975, pp. 348–355

    Google Scholar 

  6. Vishkin, U.: An Optimal Connectivity Algorithm, preprint, 1985

    Google Scholar 

  7. Valiant, L.G., Skyum, S., Berkowitz, S., Rackoff, C.: Fast Parallel Computation of Polynomials Using few Processors, SIAM J. Computing, 12, No. 4, 1983, pp. 641–644

    Google Scholar 

  8. Wald, I.: Automatische Parallelisierung von Registermaschinen, Diplomarbeit, J. W. G.-Universität Frankfurt, Fb. 20-Informatik, 1987

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Robert Cori Martin Wirsing

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Wald, I. (1988). An automatic speed-up of random access machines with powerful arithmetic instructions. In: Cori, R., Wirsing, M. (eds) STACS 88. STACS 1988. Lecture Notes in Computer Science, vol 294. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0035837

Download citation

  • DOI: https://doi.org/10.1007/BFb0035837

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18834-6

  • Online ISBN: 978-3-540-48190-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics