Abstract
Synapse matrices can be considered as basic building blocks for hardware emulators of Artificial Neural Networks. A great number of today's models use weighted sums in partial or fully connected artificial neurons; these computations being efficiently carried out by analog CMOS current-mode circuits. In this communication several alternative analog CMOS multipliers, as basic cells for synapse matrices with dynamically programmable weights, are summarised; and an enhanced implementation of such cells is presented. A chip including a 8×16 multiplier synapse matrix has been manufactured using a conventional 2µm CMOS process. The synaptic weights are dynamically modifiable and temporary memorized as analog voltages in the capacitive gates of MOS transistors. While maintaining simplicity, the basic cell in the matrix preserves the stored weight against input/outputs changes. The designed prototype has a density of 50 synapses per square millimetre, including the circuitry for individual weight actualization of each synapse in the matrix. Some experimental results demonstrating the functionality of the circuit are also reported.
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Pelayo, F.J., Pino, B., A, P., Ortega, J., Fernandez, F.J. (1991). Cmos implementation of synapse matrices with programmable analog weights. In: Prieto, A. (eds) Artificial Neural Networks. IWANN 1991. Lecture Notes in Computer Science, vol 540. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0035907
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DOI: https://doi.org/10.1007/BFb0035907
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