Abstract
A brief introduction is made of the Backpropagation algorithm and its parallelization in a proposed architecture. The main requirements of each of the architecture's processors is then elaborated and the final Integrated Circuit design presented. Each part of the processor is discussed separately: ALU, communications unit, memory and the control unit. The control unit is discussed with more detail by explaining how it performs when doing the emulation.
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VI. References
F.Castillo, J.Cabestany, "A VLSI Neural Net Architecture — A Proposal", Proc. Neuro-Nîmes'90.
F.Castillo, J.M.Moreno, J.Cabestany, "Digital VLSI Implementation of a Neural Processor", Proc. Melecon '91, Yugoslavia.
F.Castillo, P.Amengual, J.Cabestany, "A Sensibility Study of the Backpropagation Algorithm", Proc. ICANN'91, Helsinki.
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© 1991 Springer-Verlag Berlin Heidelberg
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Castillo, F., Cabestany, J., Moreno, J.M. (1991). An integrated circuit for artificial neural networks. In: Prieto, A. (eds) Artificial Neural Networks. IWANN 1991. Lecture Notes in Computer Science, vol 540. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0035910
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DOI: https://doi.org/10.1007/BFb0035910
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