Abstract
This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.
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© 1998 Springer-Verlag Berlin Heidelberg
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de Souza, A.F., Rounce, P. (1998). Dynamically trace scheduled VLIW architectures. In: Sloot, P., Bubak, M., Hertzberger, B. (eds) High-Performance Computing and Networking. HPCN-Europe 1998. Lecture Notes in Computer Science, vol 1401. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0037255
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DOI: https://doi.org/10.1007/BFb0037255
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