Abstract
This paper presents novel design techniques for Residue Number System based systolic arrays for arithmetic computation useful in digital signal processing applications. Design of a 5-bit pipelined adder is explained with emphasis on the basic systolic cell design, use of clocks, pipeline techniques, simulation, and layout optimization. This pipelined adder can be used to build systolic multipliers, correlators, computational structures for DFT, etc.
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8. References
G.A. Jullien,” Residue Number Scaling and Other Operations Using ROM Arrays”, IEEE Transactions on Computers, Vol.C-27, No.4, pp.191–201, April 1977.
Paruvachi V.R. Raja, “Custom Design of CMOS ROMs for VLSI RNS hardware”, Thesis, University of Windsor, Ontario, Canada, 1988.
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M.A.Bayoumi, G.A. Jullien, and W.C.Miller, “Models for VLSI implementation of Residue Number Systems”, Proc. of 6th symposium on Computer arithmetic, 1983, pp. 174–182.
G.A. Jullien, et.al, “A VLSI Systolic Quadratic Residue DFT with fault tolerance”, ISCAS'88, pp.2271–2274, Glascow, Scotland, 1988.
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© 1991 Springer-Verlag Berlin Heidelberg
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Raja, P.V.R. (1991). Novel design techniques for RNS systolic VLSI arrays. In: Sherwani, N.A., de Doncker, E., Kapenga, J.A. (eds) Computing in the 90's. Great Lakes CS 1989. Lecture Notes in Computer Science, vol 507. Springer, New York, NY. https://doi.org/10.1007/BFb0038494
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DOI: https://doi.org/10.1007/BFb0038494
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