Abstract
It is well known that renaming is an important tool for enhancing parallelization. However, at the fine-grain level renaming involves the addition of extra registers which may affect register allocation. Thus a tradeoff between register allocation and parallelism has to be made to optimize the code performance for fine-grain parallel machines (i.e. pipelined, VLIW's, superscalars). Because of the complexity involved, previous compilers have avoided making this tradeoff by separating register allocation from code reorganization (scheduling). Unfortunately, this separation' can lead to severe performance problems. We propose in this paper a new approach which circumvents these traditional problems while yielding an efficient implementation. Some benchmarks are used to illustrate the effect of our technique.
This work was supported in part by ONR grant N00014-91-J-1406 and NSF grant CCR8996124.
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Nicolau, A., Potasman, R., Wang, H. (1992). Register allocation, renaming and their impact on fine-grain parallelism. In: Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1991. Lecture Notes in Computer Science, vol 589. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0038667
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DOI: https://doi.org/10.1007/BFb0038667
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