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Efficient reconfiguration of VLSI arrays

Extended abstract

  • Simulation And Embedding Of Parallel Networks
  • Conference paper
  • First Online:
VLSI Algorithms and Architectures (AWOC 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 319))

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Abstract

We consider the problem of reconfiguring a 2-dimensional VLSI array with faulty cells. A network flow model of the problem is formulated and an algorithm is presented for interconnecting the functional cells of the array so that they simulate a fault-free array of smaller size. Experimental results on the practical performance of this algorithm and of other techniques previously proposed in the literature are reported.

Research partially supported by the Joint Services Electronics Program under Contract N00014-84-C-0149. Portions of this work were done while the first author was visiting the Coordinated Science Laboratory of the University of Illinois.

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References

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Author information

Authors and Affiliations

  1. Istituto di Elaborazione dell'Informazione, Consiglio Nazionale delle Ricerche, 56100, Pisa, Italy

    Bruno Codenotti

  2. Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 61801, Urbana, Illinois

    Roberto Tamassia

Authors
  1. Bruno Codenotti
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  2. Roberto Tamassia
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Editor information

John H. Reif

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© 1988 Springer-Verlag Berlin Heidelberg

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Codenotti, B., Tamassia, R. (1988). Efficient reconfiguration of VLSI arrays. In: Reif, J.H. (eds) VLSI Algorithms and Architectures. AWOC 1988. Lecture Notes in Computer Science, vol 319. Springer, New York, NY. https://doi.org/10.1007/BFb0040387

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  • DOI: https://doi.org/10.1007/BFb0040387

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-0-387-96818-6

  • Online ISBN: 978-0-387-34770-7

  • eBook Packages: Springer Book Archive

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