Abstract
Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. But the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. Loop statements in traditional programs consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This paper develops a formal methodology for mapping loops onto reconfigurable architectures. We develop a parameterized abstract model of reconfigurable architectures which is general enough to capture a wide range of configurable systems. Our abstract model is used to define and solve the problem of mapping loop statements onto reconfigurable architectures. We show a polynomial time algorithm to compute the optimal sequence of configurations for one important variant of the problem. We illustrate our approach by showing the mapping of an example loop statement.
This work was supported by the DARPA Adaptive Computing Systems Program under contract DABT63-96-C-0049 monitored by Fort Hauchuca.
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References
K. Bondalapati and V.K. Prasanna. Reconfigurable Meshes: Theory and Practice. In Reconfigurable Architectures Workshop, RAW'97, Apr 1997.
Kiran Bondalapati and Viktor K. Prasanna. The Hybrid System Architecture Model (HySAM) of Reconfigurable Architectures. Technical report, Department of Electrical Engineering-Systems, University of Southern California, 1998.
D. A. Buell, J. M. Arnold, and W. J. Kleinfelder. Splash 2: FPGAs in a Custom Computing Machine. IEEE Computer Society Press, 1996.
S. Choi and V.K. Prasanna. Configurable Hardware for Symbolic Search Operations. In International Conference on Parallel and Distributed Systems, Dec 1997.
Y. Chung and V.K. Prasanna. Parallel Object Recognition on an FPGA-based Configurable Computing Platform. In International Workshop on Computer Architectures for Machine Perception, Oct 1997.
A. Dandalis and V.K. Prasanna. Fast Parallel Implementation of DFT using Configurable Devices. In 7th International Workshop on Field-Programmable Logic and Applications, Sept 1997.
J. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 12–21, April 1997.
R. Kress, R.W. Hartenstein, and U. Nageldinger. An Operating System for Custom Computing Machines based on the Xputer Paradigm. In 7th International Workshop on Field-Programmable Logic and Applications, pages 304–313, Sept 1997.
A. Lawrence, A. Kay, W. Luk, T. Nomura, and I. Page. Using reconfigurable hardware to speed up product development and performance. In 5th International Workshop on Field-Programmable Logic and Applications, 1995.
W. Luk, N. Shirazi, S.R. Guo, and P.Y.K. Cheung. Pipeline Morphing and Virtual Pipelines. In 7th International Workshop on Field-Programmable Logic and Applications, Sept 1997.
P. Lysaght and J. Stockwood. A Simulation Tool for Dynamically Reconfigurable FPGAs. IEEE Transactions on VLSI Systems, Sept 1996.
Xilinx DSP Application Notes. The Fastest FFT in the West, http://www.xilinx.com/apps/displit.htm.
R.J. Petersen and B. Hutchings. An Assessment of the Suitability of FPGA-Based Systems for use in Digital Signal Processing. In 5th International Workshop on Field-Programmable Logic and Applications, 1995.
S. Trimberger, D. Carberry, A. Johnson, and J. Wong. A Time-Multiplexed FPGA. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 22–28, April 1997.
NSC NAPA 1000 URL. http://www.national.com/appinfo/milaero/napa1000/.
J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard. Programmable Active Memories: Reconfigurable Systems Come of Age. IEEE Transactions on VLSI Systems, 4(1):56–69, March 1996.
M. Weinhardt. Compilation and Pipeline Synthesis for Reconfigurable Architectures. In Reconfigurable Architectures Workshop RAW'97. ITpress Verlag, Apr 1997.
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Bondalapati, K., Prasanna, V.K. (1998). Mapping loops onto reconfigurable architectures. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055254
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DOI: https://doi.org/10.1007/BFb0055254
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