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Computing Goldbach partitions using pseudo-random bit generator operators on an FPGA systolic array

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Field-Programmable Logic and Applications From FPGAs to Computing Paradigm (FPL 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1482))

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Abstract

Calculating the binary Goldbach partitions for the first 128× 106 numbers represents weeks of computation with the fastest microprocessors. This paper describes an FPGA systolic implementation for reducing the execution time. High clock frequency is achieved using operators based on pseudo-random bit generator. Experiments carried both on the R10000 processor and on the FPGA PeRLe-1 board are reported.

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References

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Author information

Authors and Affiliations

  1. IRISA, Campus de Beaulieu, 35042, Rennes, France

    Dominique Lavenier

  2. IRIT, 118 route de Narbonne, 31062, Toulouse, France

    Yannick Saouter

Authors
  1. Dominique Lavenier
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  2. Yannick Saouter
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Editor information

Reiner W. Hartenstein Andres Keevallik

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© 1998 Springer-Verlag Berlin Heidelberg

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Lavenier, D., Saouter, Y. (1998). Computing Goldbach partitions using pseudo-random bit generator operators on an FPGA systolic array. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055259

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  • DOI: https://doi.org/10.1007/BFb0055259

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64948-9

  • Online ISBN: 978-3-540-68066-6

  • eBook Packages: Springer Book Archive

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