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Maestro-link: A high performance interconnect for PC cluster

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Field-Programmable Logic and Applications From FPGAs to Computing Paradigm (FPL 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1482))

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Abstract

Maestro is a distributed shared memory system currently being developed. In this paper, an architecture of the high performance network interface of Maestro is presented. Maestro consists of multiple PC(Personal Computers and dedicated network hardware for high performance message passing and maintaining cache coherency. IEEE1394, a high performance serial link, is used in the physical layer of Maestro network. The network interface is developed using FPGA(Field Programmable Gate Array)s. A network latency and a bandwidth between the network interface and PC are measured and discussed.

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Author information

Authors and Affiliations

  1. Institute of Information Sciences and Electronics, University of Tsukuba, Tsukuba, 305, Ibaraki, Japan

    Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota & Koichi Wada

Authors
  1. Shinichi Yamagiwa
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  2. Masaaki Ono
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  3. Takeshi Yamazaki
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  4. Pusit Kulkasem
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  5. Masayuki Hirota
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  6. Koichi Wada
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Editor information

Reiner W. Hartenstein Andres Keevallik

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© 1998 Springer-Verlag Berlin Heidelberg

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Yamagiwa, S., Ono, M., Yamazaki, T., Kulkasem, P., Hirota, M., Wada, K. (1998). Maestro-link: A high performance interconnect for PC cluster. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055273

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  • DOI: https://doi.org/10.1007/BFb0055273

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64948-9

  • Online ISBN: 978-3-540-68066-6

  • eBook Packages: Springer Book Archive

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