Abstract
Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XCAOxx — 5 FPGAs.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. V. Openheim, R. W. Schafer: Digital Signal Processing, Prentice Hall (1975)
P. Pirsch: Architectures for Digital Signal Processing, John Wiley & Sons (1997)
Xilinx Inc.: The Programmable Logic Data Book, (1996)
L. Mintzer: FIR Filters with Field-Programmable Gate Arrays, IEEE Journal of VLSI Signal Processing (August 1993) 119–128
C. S. Burrus: Digital Filters Structures described by Distributed Arithmetic, IEEE Trans. on Circuits and Systems (1977), 674–680
Xilinx Inc.: Core Solutions, (May 1997)
T.-T. Do, H. Kropp, M. Schwiegershausen, P. Pirsch: Implementation of Pipelined Multipliers on Xilinx FPGAs — A Case Study, 7th International Workshop on Field-Programmable Logic and Applications, Proceedings (1997)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Do, TT., Kropp, H., Reuter, C., Pirsch, P. (1998). A flexible implementation of high-performance FIR filters on Xilinx FPGAs. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055277
Download citation
DOI: https://doi.org/10.1007/BFb0055277
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-64948-9
Online ISBN: 978-3-540-68066-6
eBook Packages: Springer Book Archive