Space-efficient mapping of 2D-DCT onto dynamically configurable coarse-grained architectures

Abstract

This paper shows an efficient design for 2D-DCT on dynamically configurable coarse-grained architectures. Such coarse-grained architectures can provide improved performance for computationally demanding applications as compared to fine-grained FPGAs. We have developed a novel technique for deriving computation structures for two dimensional homogeneous computations. In this technique, the speed of the data channels is dynamically controlled to perform the desired computation as the data flows along the array. This results in a space efficient design for 2D-DCT that fully utilizes the available computational resources. Compared with the state-of-the-art designs, the amount of local memory required is reduced by 33% while achieving the same high throughput.

This research was performed as part of the MAARC project (Models, Algorithms and Architectures for Reconfigurable Computing, http://maarc.usc.edu). This work is supported by the DARPA Adaptive Computing Systems program under contract no. DABT63-96-C-00049 monitored by Fort Hauchuca.