Generating layouts for self-implementing modules

Abstract

Recent advances in FPGA density allow system-level implementations in programmable logic. However, traditional FPGA design tools do not scale well to large complex designs containing substantial datapaths, control logic, and memories, in part because they mostly ignore hierarchy and treat complex circuits as flat netlists. Many FPGA designers have adopted synthesis-based approaches to deal with design complexity, but unfortunately, synthesis technology is not sufficiently advanced to make best use of the target FPGA. As a result, libraries of modules with optimized implementations are essential for high-performance system-level FPGA design [1], [2], [3]. In this paper we describe an object-oriented framework for module generation, focusing on a novel approach to specifying and computing layouts for parametric modules.