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Load balancing in parallel circuit testing with annealing-based and genetic algorithms

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Parallel Problem Solving from Nature — PPSN V (PPSN 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1498))

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Abstract

A new combination of Simulated Annealing and Tabu Search is presented for load balancing in a parallel circuit testing procedure. The testing procedure requires a circuit partitioning algorithm to distribute the workload among the processors in such a way that similar sized parts of the circuit are assigned to each processor while communications are minimised. The hybrid algorithm for circuit partitioning is compared with pure tabu search and simulated annealing algorithms, and also with a genetic algorithm. The solutions obtained are evaluated for the circuits of a frequently used benchmark set.

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Author information

Authors and Affiliations

  1. Dept. de Arquitectura de Computadores y Electrónica, Univ. Almería, Spain

    C. Gil & M. G. Montoya

  2. Dept. de Arquitectura y Tecnología de Computadores, Univ. Granada, Spain

    J. Ortega, A. F. Díaz & A. Prieto

Authors
  1. C. Gil
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  2. J. Ortega
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  3. A. F. Díaz
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  4. M. G. Montoya
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  5. A. Prieto
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Editor information

Agoston E. Eiben Thomas Bäck Marc Schoenauer Hans-Paul Schwefel

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© 1998 Springer-Verlag Berlin Heidelberg

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Gil, C., Ortega, J., Díaz, A.F., Montoya, M.G., Prieto, A. (1998). Load balancing in parallel circuit testing with annealing-based and genetic algorithms. In: Eiben, A.E., Bäck, T., Schoenauer, M., Schwefel, HP. (eds) Parallel Problem Solving from Nature — PPSN V. PPSN 1998. Lecture Notes in Computer Science, vol 1498. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0056925

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  • DOI: https://doi.org/10.1007/BFb0056925

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65078-2

  • Online ISBN: 978-3-540-49672-4

  • eBook Packages: Springer Book Archive

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