Abstract
The Counterflow Pipeline (CFP) organization may be a good target for synthesis of application-specific microprocessors for embedded systems because it has a regular and simple structure. This paper describes a design environment for tailoring CFP’s to an embedded application to improve performance. Our system allows exploring the design space of all possible CFP’s for a given application to understand the impact of different design decisions on performance. We have used the environment to derive heuristics that help to find the best CFP for an application. Preliminary results using our heuristics indicate that speedup for several small graphs range from 1.3 to 2.0 over a general-purpose CFP and that the heuristics find designs that are within 10% of optimal.
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© 1998 Springer-Verlag Berlin Heidelberg
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Childers, B.R., Davidson, J.W. (1998). A design environment for counterflow pipeline synthesis. In: Mueller, F., Bestavros, A. (eds) Languages, Compilers, and Tools for Embedded Systems. LCTES 1998. Lecture Notes in Computer Science, vol 1474. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0057793
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DOI: https://doi.org/10.1007/BFb0057793
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