Abstract
For the evaluation of HPC systems for real-time signal processing, real-time benchmarks have recently been proposed by the US DoD signal processing and HPC communities. For the implementation of real-time benchmarks, we have developed efficient communication algorithms for M-to-N K-block-cyclic communication. Using our algorithms, we have implemented real-time 2D-FFT and Corner Turn benchmarks that have been defined by MITRE and Rome Lab on SP2 and T3E. Our results show that the number of processors required to perform the 2D-FFT benchmark was reduced by up to 53% compared with earlier implementation. The total corner turn time was also reduced by up to 78%. The performance of IBM SP2 and SGI/Cray T3E are compared using these benchmarks.
Effort sponsored by the Dod High Performance Computing Modernization Office, and Rome Laboratory, Air Force Materiel Command, USAF, under agreement number F30602-97-2-0016. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright annotation thereon.
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© 1998 Springer-Verlag Berlin Heidelberg
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Suh, J., Prasanna, V.K. (1998). Portable implementation of real-time signal processing benchmarks on HPC platforms. In: Kågström, B., Dongarra, J., Elmroth, E., Waśniewski, J. (eds) Applied Parallel Computing Large Scale Scientific and Industrial Problems. PARA 1998. Lecture Notes in Computer Science, vol 1541. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0095378
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DOI: https://doi.org/10.1007/BFb0095378
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