Configuration sequencing with self configurable binary multipliers

Abstract

In this paper we present a hardware design technique which utilises runtime reconfiguration for a particular class of applications. For a multiplication circuit implemented within an FPGA, a specific instance of multiplying by a constant provides a significant reduction of required logic when compared to the generic case when multiplying any two arbitrary values. The use of reconfiguration allows the specific constant value to be updated, such that at any time instance the constant multiplication value will be fixed, however over time this constant value can change via reconfiguration. Through investigation and manipulation of the sequence of required multiplication operations for given applications, sequences of multiplication operations can be obtained where one input changes at a rate slower than the other input. That is one input to the multiplier is fixed for a set number of cycles, hence allowing it to be configured in hardware as a constant and reconfigured at the periodicity of its change. Applications such as the IDEA encryption algorithm and every cycle Adaptive FIR filtering are presented which utilise this reconfiguration technique providing reduced logic implementations while not compromising the performance of the design.