Abstract
Taking as a starting point for FPGAs design and efficient bit-level systolic algorithm facilitates the design process but does not automatically guarantee the most efficient hardware solution. We demonstrate on an example of Montgomery exponentiation a role of partitioning in mapping of linear systolic arrays onto Xilinx XC6000 FPGAs.
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References
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© 1999 Springer-Verlag
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Tiountchik, A., Trichina, E. (1999). Implementation of montgomery exponentiation on fine grained FPGAs: A note on partitioning. In: Sloot, P., Bubak, M., Hoekstra, A., Hertzberger, B. (eds) High-Performance Computing and Networking. HPCN-Europe 1999. Lecture Notes in Computer Science, vol 1593. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0100714
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DOI: https://doi.org/10.1007/BFb0100714
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