Abstract
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that 1-port large shared cache achieves the best performance if there is no delay penalty for arbitration and accessing the bus. However, if 1-clock delay is assumed for accessing the shared cache, a snoop cache with internal wide bus and invalidate style NewKeio protocol overcomes shared caches.
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© 1997 Springer-Verlag Berlin Heidelberg
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Kisuki, T., Wakabayashi, M., Yamamoto, J., Inoue, K., Amano, H. (1997). Shared vs. snoop: Evaluation of cache structure for single-chip multiprocessors. In: Lengauer, C., Griebl, M., Gorlatch, S. (eds) Euro-Par'97 Parallel Processing. Euro-Par 1997. Lecture Notes in Computer Science, vol 1300. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0002815
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DOI: https://doi.org/10.1007/BFb0002815
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