Abstract
Recently discovered lower bounds for the area-time complexity of VLSI sorting of n k -bit keys exhibit a dependence upon the key length. On this basis, keys can be classified into short (k ≤logn), long (k ≥logn) and intermediate-length. Intermediate-length keys have been heretofore the object of investigation; this paper investigates the other two cases and confirms the inherent validity of the bounds for short and long keys by exhibiting optimal or near-optimal VLSI networks.
EXTENDED ABSTRACT
This work was supported in part by an IBM predoctoral fellowship and by NSF grant ECS-84-10902.
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References
C. D. Thompson, “A Complexity Theory for VLSI,“ Ph.D. Thesis, Dept. of Comp. Science, Carnegie-Mellon Univ.; August 1980.
R. P. Brent and H. T. Kung, “The chip complexity of binary arithmetic,“ Journal of the ACM, vol. 28, n. 3, pp. 521–534; July 1981.
J. Vuillemin, “A combinatorial limit to the computing power of VLSI circuits,“ IEEE Trans. on Comp. vol. C-32, n. 3, pp. 294–300, March 1983.
G. Bilardi and F. P. Preparata, “Square tessellation techniques for area-time lower bounds,“ submitted for publication.
G. Bilardi, “The Area-Time Complexity of Sorting,“ Ph.D. Thesis, Univ. of Illinois, 1984.
J. D. Ullman, Computational Aspects of VLSI, Computer Science Press; 1983.
F. T. Leighton, “Tight bounds on the complexity of parallel sorting,“ Proc. 16th Annual ACM Symposium on Theory of Computing, Washington, D. C., pp. 71–80; April 1984. (Also IEEE Trans. on Comp. April 1985).
A. Siegel, “Optimal area VLSI circuits for sorting,“ submitted for sub. publication.
C. D. Thompson, The VLSI complexity of sorting, IEEE Trans. Comp., vol. C-32, n. 12, pp. 1171–1184; Dec. 1983.
G. Bilardi and F. P. Preparata, “An architecture for bitonic sorting with optimal VLSI performance,“ IEEE Trans. Comp., vol. C-33, n. 7, pp. 640–651; July 1984.
G. Bilardi and F. P. Preparata, “A minimum area VLSI network for O(logN) time sorting”, Proc. 16th Annual ACM Symposium on Theory of Computing, Washington, D. C., pp. 64–70; April 1984. (Also see IEEE Trans. on Comp. April 1985.)
G. Bilardi and F. P. Preparata, “The VLSI optimality of the AKS sorting network,“ Information Processing Letters, to appear.
R. B. Johnson, “The complexity of a VLSI adder,“ Information Processing Letters, vol. 11, n. 2, pp. 92–93; October 1980.
G. M. Baudet, “On the area required by VLSI circuits,“ manuscript.
A. Siegel, “Minimal Storage Sorting Circuits,“ IEEE Trans. Comp., vol. C-34, n. 4; April 1985.
R. Cole and A. Siegel, “Optimal VLSI network that sort a numbers in an arbitrary, fixed range”, manuscript.
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Bilardi, G., Preparata, F.P. (1985). The influence of key length on the area-time complexity of sorting. In: Brauer, W. (eds) Automata, Languages and Programming. ICALP 1985. Lecture Notes in Computer Science, vol 194. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0015730
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DOI: https://doi.org/10.1007/BFb0015730
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