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A system for designing parallel processor arrays

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Computer Aided Systems Theory — EUROCAST'97 (EUROCAST 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1333))

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Abstract

In this paper a system for the design of massively parallel processor arrays is presented. We describe new methods for the consideration of hardware constraints and of performance criteria in the design process. In particular, we focus on the determination of a full size array for the original algorithm which we want to implement in silicon. The arising optimization problems can be solved using integer linear programming. Furthermore, we describe methods for adapting the full size arrays to hardware constraints of a target architecture which is embedded in a peripheral system.

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Author information

Authors and Affiliations

  1. Systems Theory, Institute of Circuits and Systems, University of Technology Dresden, Mommsenstr.13, 01062, Dresden, Germany

    R. Merker, U. Eckhardt, D. Fimmel & H. Schreiber

Authors
  1. R. Merker
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  2. U. Eckhardt
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  3. D. Fimmel
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  4. H. Schreiber
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Editor information

Franz Pichler Roberto Moreno-Díaz

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© 1997 Springer-Verlag Berlin Heidelberg

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Merker, R., Eckhardt, U., Fimmel, D., Schreiber, H. (1997). A system for designing parallel processor arrays. In: Pichler, F., Moreno-Díaz, R. (eds) Computer Aided Systems Theory — EUROCAST'97. EUROCAST 1997. Lecture Notes in Computer Science, vol 1333. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0025030

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  • DOI: https://doi.org/10.1007/BFb0025030

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63811-7

  • Online ISBN: 978-3-540-69651-3

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