Abstract
Image Processing and Pattern Recognition (IPPR) is receiving new impulse from the progress of Instruction Level Parallel (ILP) architectures which in general exhibit a level of performance comparable with that of the previous decade supercomputers. However, in spite of the huge computing power in principle available, it is a common experience that ILP efficiency in IPPR turns out to be low.
In this paper we describe the sources of inefficiency of ILP in IPPR and define a set of indices that allows analyzing them quantitatively. The quantitative analysis of the sources of inefficiency can be used by applications software developers to identify the most convenient coding solutions for IPPR algorithms (e.g. loop unrolling, loop permutation, register assignment) as well as to assess the advantages of such solutions over the natural and straightforward transposition of the algorithms in programs.
This work was supported by European Community through the ESPRIT BRA Project 8849-SM-IMP and by MURST.
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© 1997 Springer-Verlag Berlin Heidelberg
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Migliardi, M., Maresca, M. (1997). Modeling Instruction Level Parallel architectures efficiency in image processing applications. In: Hertzberger, B., Sloot, P. (eds) High-Performance Computing and Networking. HPCN-Europe 1997. Lecture Notes in Computer Science, vol 1225. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031645
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DOI: https://doi.org/10.1007/BFb0031645
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