Abstract
We present an open environment for the integration of formal methods applied to HDL descriptions of circuits. The system currently accepts SMAX[4] and VHDL, and provides equivalence checking, model checking, theorem proving, and automatic diagnosis of simple design errors. After an overview of the system, we discuss the salient features of the common intermediate format, of the diagnosis tools, and of the automatic generation of NQTHM[11] models from VHDL functional descriptions.
Preview
Unable to display preview. Download preview PDF.
References
IEEE: “Standard VHDL Language Reference Manual”, IEEE Standard 1076-1993 1993
Thomas D. E., Moorby P. R.: “The Verilog Hardware Description Language”, Second edition, Kluwer, 1995
Borrione D., Pierre L., Salem A.: “Formal verification of VHDL Descriptions in the Prevail Environment”, IEEE Design and Test of Computers, Vol 9, Nℴ2, pp. 42–56, 1992
Eveking H.: “Axiomatizing hardware description languages”. International Journal of VLSI Design, Vol. 2, Nℴ 3, pp. 263–280, 1990.
A.Bartsch, H.Eveking, H.J.Faerber, M.Kelelatchew, J.Pinder, U.Schellin: “LOVERT-A Logic Verifier of Register-Transfer Descriptions”. In Formal VLSI Correctness Verification, L.Claesen Ed., North Holland (1990), ISBN 0444 88689 3.
O.Coudert, C.Berthet, J.C.Madre: “Verification of synchronous sequential machines based on symbolic execution”. In Automatic Verification Methods for Finite State Systems, LNCS nℴ407. Spinger Verlag 1989 (pp 365–373).
J.R.Burch, E.M.Clarke, K.L.McMillan, D.L.Dili: “Sequential circuit verification using symbolic model ckecking”, Proc. 27th Design Automation Conf, 1990.
Clarke E.M., Emerson E.A., Sistla A.P.: “Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications”, ACM Trans. on Programming Languages and Systems, Vol 8, Nℴ 2, pp. 244–263, 1986.
Deharbe D., Borrione D.: “Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms”. Current Issues in Electronic Modeling, Vol 1 on Model Generation in Electronic Design, Kluwer, March 1995.
Höreth S.: “Improving the performance of a BDD-based tautology checker,” Proc. Advanced Research Workshop on Correct Hardware Design Methodology, Turin, North-Holland, 1991
Boyer R. S., Moore J. S.: “A Computational Logic Handbook ”, Academic Press Inc., 1988
Hunt W.A.: “FM8501: A Verified Microprocessor”, Technical Report 47, University of Texas at Austin, 1986
Wahba A., Borrione D.: “A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits”, to appear in Journal of Electronic Testing: Theory and Applications, Kluwer.
Wahba A., Borrione D.: “Design error diagnosis in sequential circuits.” Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Frankfurt, 2–4 October 1995. LNCS, Springer Verlag.
Debreil A., Oddo P.: “Synchronous Designs in VHDL”, Proc. EuroDAC/EuroVHDL, pp.486–491, 1993
Deharbe D., Borrione D.: “Semantics of a verification. Oriented subset of VHDL.” Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Frankfurt, 2–4 October 1995. LNCS, Springer Verlag.
Bouamama H, Borrione D.: “VHDL subset for parameterized models: the proof-oriented intermediate form Version 1.1”, technical report, JESSI-AC3, 1994
L. Yang, D. Gao, J. Mostoufi, R. Joshi, and P. Loewenstein, “System Design Methodology of UltraSPARCℳ-I,” Proceedings of the 32nd Design Automation Conference DAC'95, pp. 7–12, 1995.
T. W. Albrecht, “Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD-CCS7E Processor System Simulation,” Proceedings of the 32nd Design Automation Conference DAC'95, pp. 222–227, 1995.
A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek, “Test Program Generation for Functional Verification of PowerPC Processors in IBM,” Proceedings of the 32nd Design Automation Conference DAC'95, pp. 279–285, 1995.
M. S. Abadir, J. Ferguson, and T. E. Kirkland, “Logic Design Verification via Test Generation,” IEEE Transactions on Computer-Aided Design, Vol. 7, No. 1, pp. 138–148, Jan. 1988.
M. R. Garey, and D. S. Johnson, “Computers and Interactibility: A Guide to the Theory of NP-Completeness,” Freeman, New York, 1979.
E. J. Aas, K. A. Klingsheim, and T. Steen, “Quantifying Design Quality: A Model and Design Experiments,” Proc. EURO-ASIC'92, pp. 172–177, 1992.
F. Brglez, and H. Fujiwara, “A neutral netlist of 10 combinatorial benchmark circuits and a target translator in FORTRAN,” in Proc. IEEE Int. Symp. Circuits and Systems, pp. 663–698, June 1985.
F. Brglez, D. Bryan and K. Kozminski, “Combinational Profiles of Sequential Circuits,” Proc. IEEE International Symposium of Circuits and Systems (ISCAS'89), Portland, OR, May 1989.
Borrione D., Bouamama H., Suescun R.; “NQTHM Library for VHDL”, JESSI-AC3 Tech. Report, 1995
CLSI-Solutions: “VFORMAL User's Manual”, Version 1.0, 1993
D.Eisenbiegler, R. Kumar, and J. Muller, “A Formal Model for a VHDL Subset of Synchronous Circuits”, in Proc. of APCHDL'96, Bengalore, India
D. Déharbe: “The CV system”. URL http://www.cs.cmu.edu/∼deharbe/project.html
Olcoz S., Colom J.M.: “A Colored Petri Net Model of VHDL”, Formal Methods in System Design, Vol 7, Nℴ 1–2, pp. 101–123, 1995.
E. Encrenaz: “Une methode de verification de propriétés de programmes VHDL basée sur des modèles formels de reseaux de Petri”, PhD Thesis, Universite Paris VI, Dec 1995 (in French)
M. Belhadj: “Conception d'architectures en utilisant SIGNAL et VHDL”, PhD Thesis, Universite de Rennes 1, Dec. 1994 (in French)
J.P. van Tassel: “Femto-VHDL: The semantics of a subset of VHDL and its embedding in the HOL theorem prover”, PhD thesis, University of Cambridge, 1993
G. Humbreit: “Providing a VHDL interface for proof systems”, Proc. EDAC, Paris, 1992
D. Russinoff: “A formalization of a subset of VHDL in the Boyer-Moore Logic”, Formal Methods in System Design, Vol 7, No 1/2, Kluwer, August 1995
R. Brayton et al.: “VIS: A System for Verification and Synthesis”, Proc. Computer Aided Verification, CAV'96 (to appear)
VIS Development Group: “Description of BLIF-MV, An Intermediate Format for Verification and Synthesis of Hierarchical Networks of FSMs”, Tech. Report, U.C. Berkeley, CAD Group, hhtp://www-cad.eecs.berkeley.edu/Respep/Research/vis
K.L.McMillan: private communication.
W. Damm, G. Dohmen, P. Kelb, H. Pargmann, R. Schlör, R. Herrmann: “Verification Flow”, Seminar 5 on “Specification and verification of VHDL-based System-level Hardware Designs” Proc. of APCHDL'96, Bengalore, India
J. Lohse, J. Bormann, M. Payer, G.Venzl: “VHDL-Translation for BDD-based Formal Verification”. Siemens Internal Report, München, Germany, 1994.
J. Bormann, J.Lohse, M. Payer and G.Venzl: “Model Checking in Industrial Hardware Design”, Proc of DAC' 95.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Borrione, D., Bouamama, H., Deharbe, D., Le Faou, C., Wahba, A. (1996). HDL-based integration of formal methods and CAD tools in the PREVAIL environment. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031827
Download citation
DOI: https://doi.org/10.1007/BFb0031827
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61937-6
Online ISBN: 978-3-540-49567-3
eBook Packages: Springer Book Archive