A cryptanalysis of clock-controlled shift registers with multiple steps

Abstract

A clock-controlled shift register that is clocked at least once and at most d + 1 times per output symbol is cryptanalyzed using a constrained embedding approach. Upper bounds on the constrained embedding probabilities that are exponentially small in the string length are derived using finite automata theory and generating functions. A known constrained embedding divide-and-conquer attack on a clock-controlled shift-register developed for at most two clocks at a time (d=1) is thus extended to the general case of arbitrary d. The results show that the minimum length of the observed output sequence needed for successful initial state reconstruction is linear in the shift register length, and at least exponential and at most superexponential in d. This proves that by making d large one cannot achieve the theoretical security against the embedding attack. Experimental results obtained by computer simulations indicate that the required output sequence length is only exponential in d, which would mean that the embedding attack is feasible if d is not too large.

This research was supported in part by the Science Fund of Serbia, grant #0403, through the Institute of Mathematics, Serbian Academy of Arts and Sciences.

The work reported in this paper has been funded in part by the Cooperative Research Centres program through the Department of the Prime Minister and Cabinet of Australia.