Abstract
In this paper we study positioning strategies for improving the performance of a memory system with a direct mapped cache. A positioning technique determines for every program item, (instruction or data), its address in main memory.
Assuming the Independent Reference Model, we break the general positioning problem into two: the collision minimization, and the grouping problems; and show optimal algorithms for both problems. Using these algorithms we derive an optimal algorithm for the general positioning problem. Also, we show that the quality of a class of natural assignments that distribute the items almost arbitrarily is good as long as the optimal hit ratio is sufficiently large. For the case of more restricted positionings, we find an optimal assignment for the special case of the pair assignment.
In addition we look at the expected performance gain of two frequently suggested cache features. The cache bypass feature supports the access of items in memory without loading the item into the cache. We show an assignment with best possible hit ratio which is almost always better then the optimal hit ratio. Also, it is shown that a random cache which alters the assignment of an item randomly cannot improve the expected hit ratio.
These optimal positioning algorithms can be easily integrated into an optimizing compiler. The access probabilities can be estimated statically by sophisticated compilation techniques or dynamically from traces. For programs that implement accesses to a data structure where the current step is independent of previous steps it seems that optimal hit ratio can be achieved.
Visiting AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, New Jersey
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A. Agarwal, P. Chow, M. Horowitz, J. Acken, A. Saltz, and J. Hennessy. On chip caches for high performance processors. In Proc. of Conf. on Advanced Research in VLSI, pages 1–24, Stanford Univ., Univ. of California, Berkeley, March 87. edited by P. Losleben.
P. A. Franaszek and T.J. Wagner. Some distribution free aspects of paging algorithm performance. JACM, 21(1):31–39, January 74.
Rajiv Gupta and Chi-Hung Chi. Improving instruction cache behavior by reducing cache pollution. In Proceedings Supercomputing 90, pages 82–91, November 1990.
D. J. Hartfield and J. Gerald. Program restructuring for virtual memory. IBM Systems Journal, 10(3):168–192, 1971.
S. J. Hartly. Compile-time program restructuring in multiprogrammed virtual memory systems. IEEE Trans. on SW Eng., 14(11):1640–1644, November 1988.
M. D. Hill. Aspects of Cache Memory and Instruction Buffer Performance. PhD thesis, Univ. of California, Berkeley, 1987.
Yona Hollander and Alon Itai. The offline mapping problem for direct mapped caches is NP-complete. In preparation, 91.
Scott McFarling. Program optimization for instruction caches. In Third International Conf. on Architectural Support for Programming Languages and Operating Systems, pages 183–191, April 89.
Wen mei W. Hwu and Pohua P. Chang. Achieving high instruction cache performance with an optimizing compiler. In Proc. 16th. Sym. on Computer Architecture, pages 242–250, Jerusalem, Israel, May 89.
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© 1992 Springer-Verlag Berlin Heidelberg
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Gal, S., Hollander, Y., Itai, A. (1992). Optimal mapping in direct mapped cache environments. In: Dolev, D., Galil, Z., Rodeh, M. (eds) Theory of Computing and Systems. ISTCS 1992. Lecture Notes in Computer Science, vol 601. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0035169
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DOI: https://doi.org/10.1007/BFb0035169
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