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Fast self-reduction algorithms for combinatorial problems of VLSI design

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VLSI Algorithms and Architectures (AWOC 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 319))

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Abstract

In a recent series of papers [FL1, FL2, FL3], we have proven the existence of decision algorithms with low-degree polynomial running times for a number of well-studied VLSI layout, placement and routing problems. These results make use of the powerful Robertson-Seymour theorems on the well-partial-ordering of graphs under both the minor and immersion orders. In the present paper, we study the complexity of construction versions of these problems, focusing on efficient self-reduction strategies. We introduce a notion of fast self-reduction in this setting and develop a general technique, which we term scaffolding, that is useful in the design of fast self-reduction algorithms.

This author's research is supported in part by the Sandia University Research Program and by the National Science Foundation under grant MIP-8603879.

This author's research is supported in part by the Washington State Technology Center and by the National Science Foundation under grants ECS-8403859 and MIP-8603879.

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John H. Reif

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© 1988 Springer-Verlag Berlin Heidelberg

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Fellows, M.R., Langston, M.A. (1988). Fast self-reduction algorithms for combinatorial problems of VLSI design. In: Reif, J.H. (eds) VLSI Algorithms and Architectures. AWOC 1988. Lecture Notes in Computer Science, vol 319. Springer, New York, NY. https://doi.org/10.1007/BFb0040395

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  • DOI: https://doi.org/10.1007/BFb0040395

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-0-387-96818-6

  • Online ISBN: 978-0-387-34770-7

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