Skip to main content

Time lower bounds for parallel sorting on a mesh-connected processor array

  • Parallel Routing And Sorting
  • Conference paper
  • First Online:
VLSI Algorithms and Architectures (AWOC 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 319))

Included in the following conference series:

Abstract

We prove that \((1 + \sqrt 6 /2)n\) is a time lower bound independent of indexing schemes for sorting n 2 items on an n×n mesh-connected processor array. We distinguish between indexing schemes by showing that there exists an indexing scheme which is provably worse than the snake-like row-major indexing for sorting. We also derive lower bounds for various indexing schemes. All these results are obtained by using the chain argument which we provide in this paper.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Ajtai, M., J. Komlós, and E. Szemerédi. An O(NlogN) sorting network. Proc. 15th ACM Symp. on Theory of Computing, 1–9(1983).

    Google Scholar 

  2. Bilardi, G., and Preparata, F.: A minimum area VLSI architecture for O(logN) time sorting, Proc. 16th Annual ACM Symp. on Theory of Computing, 67–70(1984).

    Google Scholar 

  3. Bitton, D., Dewitt, D.T., Hsiao, D.K., and Menon, J.: A taxonomy of parallel sorting, ACM Computing Survey, 16, 287–318 (1984).

    Article  MATH  MathSciNet  Google Scholar 

  4. Cole, R.: Parallel merge sort. 27th Symp. on Foundations of Comput. Sci., IEEE, 511–516(1986).

    Google Scholar 

  5. Han, Y., Y. Igarashi, M. Truszczynski.: Indexing schemes and lower bounds for sorting on a mesh-connected computer. manuscript.

    Google Scholar 

  6. Kunde, M.: Lower bounds for sorting on mesh-connected architectures. Acta Informatica, 24, 121–130(1987).

    Article  MATH  MathSciNet  Google Scholar 

  7. Lang, H.-W., Schimmler, M., Schmech, H. and Schröder, H.: Systolic sorting on a mesh-connected network, IEEE Trans. Comput., C-34, 652–658(1985).

    Google Scholar 

  8. Leighton, T.: Tight bounds on the complexity of parallel sorting. IEEE Trans. Comput., C-34, 344–354, 1985.

    MathSciNet  Google Scholar 

  9. Ma, Y., Sen, S. and Scherson, I.D.: The distance bound for sorting on mesh-connected processor arrays is tight. 27th Symp. on Foundations of Comput. Sci., IEEE, 255–263(1986).

    Google Scholar 

  10. Nassimi, D., and Sahni, S.: Bitonic sort on a mesh-connected parallel computer, IEEE Trans. Comput., C-27(1979).

    Google Scholar 

  11. Reif, J.H. and Valiant L.G.: A logarithmic time sort for linear size networks, J. ACM, 34, 60–76(1987).

    Article  MathSciNet  Google Scholar 

  12. Sado, K. and Igarashi, Y.: A divide-and-conquer method of the parallel sort, IECE of Japan, Tech. Commit. of Automata and Languages, AL84-68, 41–50(1985).

    Google Scholar 

  13. Sado, K. and Igarashi, Y.: A fast pseudo-merge sorting algorithm, IECE of Japan, Tech. Commit. of Automata and Languages, AL84-68, 41–50(1985).

    Google Scholar 

  14. Sado, K. and Igarashi, Y.: Fast parallel sorting on a mesh-connected processor array, Proc. of Japan-U.S. Joint Seminar, Discrete Algorithms and Complexity Theory(Johnson, D.S. et al. eds), Academic Press, New York, 161–183(1986).

    Google Scholar 

  15. Sado, K. and Igarashi, Y.: Some parallel sorts on a mesh-connected processor array, J. Parallel and Distributed Computing, Vol. 3, pp. 389–410, 1986.

    Article  Google Scholar 

  16. Scherson, I.D., Sen, S. and Shamir, A.: Shear sort: A true two-dimensional sorting technique for VLSI networks, Proc. 1986 Int. Conf. on Parallel Processing, 903–908(1986).

    Google Scholar 

  17. Schnorr, C.P. and Shamir, A.: An optimal sorting algorithm for mesh-connected computers, Proc. 18-th ACM Symp. on Theory of Computing, 255–263(1986).

    Google Scholar 

  18. Thompson, C.D. and Kung, H.T.: Sorting on a mesh-connected parallel computer, Commun. ACM, 20, 263–271(1977).

    Article  MATH  MathSciNet  Google Scholar 

  19. Thompson, C.D.: The VLSI complexity of sorting, IEEE Trans. Comput. C-32, 1171–1184(1983).

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

John H. Reif

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Han, Y., Igarashi, Y. (1988). Time lower bounds for parallel sorting on a mesh-connected processor array. In: Reif, J.H. (eds) VLSI Algorithms and Architectures. AWOC 1988. Lecture Notes in Computer Science, vol 319. Springer, New York, NY. https://doi.org/10.1007/BFb0040410

Download citation

  • DOI: https://doi.org/10.1007/BFb0040410

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-0-387-96818-6

  • Online ISBN: 978-0-387-34770-7

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics