Abstract
Floorplanning is a crucial step in the physical design flow for FPGAs. In this paper, we use min-cut based successive bipartitioning to floorplan circuits for application to FPGAs. The primary motivation of this work is reduction of execution lime required to accomplish the floorplanning step of device mapping. Our method includes clustering to enhance circuit performance and terminal propagation to reduce total wire length and enhance circuit routability. The floorplanner is intended to take predefined macro based designs as input. Using the Xilinx xc4000 series of FPGAs as the target architecture, we have demonstrated effective and fast floorplanning on a collection of designs.
This research is partially supported by contract number F33615-96-C1912 from Wright Laboratory of the US Air Force and a grant from Lucent Technologies
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© 1998 Springer-Verlag Berlin Heidelberg
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Emmert, J.M., Randhar, A., Bhatia, D. (1998). Fast floorplanning for FPGAs. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055240
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DOI: https://doi.org/10.1007/BFb0055240
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