Self modifying circuitry — A platform for tractable virtual circuitry

Abstract

The performance advantages, gained in early virtual circuitry systems, are being recouped through advances in general purpose processor architectures and have resulted in a questioning of the tractability of applying virtual circuitry in a general software environment. Two primary limitations of existing virtual circuitry systems are highlighted and the Flexible URISC is introduced as an array resident minimal processor architecture. Performance results of a prototype implementation of the Flexible URISC architecture demonstrate how peripheral bus bandwidth limitations are overcome by the increased bandwidth available to an array resident configuration, communication and computation agent. A discussion of the programming environment of the Flexible URISC is given, and provides the medium for identifying how the Flexible URISC's single instruction — move — effectively minimises the hardware/software divide.